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Jack Humbert
reform-boundary-uboot
Commits
985a71d1
Commit
985a71d1
authored
11 years ago
by
Tom Rini
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Merge branch 'master' of
git://www.denx.de/git/u-boot-ppc4xx
parents
89993dc3
9055f66c
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Changes
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2 changed files
board/lwmon5/lwmon5.c
+3
-0
3 additions, 0 deletions
board/lwmon5/lwmon5.c
include/configs/lwmon5.h
+9
-1
9 additions, 1 deletion
include/configs/lwmon5.h
with
12 additions
and
1 deletion
board/lwmon5/lwmon5.c
+
3
−
0
View file @
985a71d1
...
@@ -527,6 +527,9 @@ void spl_board_init(void)
...
@@ -527,6 +527,9 @@ void spl_board_init(void)
*/
*/
board_early_init_f
();
board_early_init_f
();
/* enable the LSB transmitter */
gpio_write_bit
(
CONFIG_SYS_GPIO_LSB_ENABLE
,
1
);
/*
/*
* Clear resets
* Clear resets
*/
*/
...
...
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include/configs/lwmon5.h
+
9
−
1
View file @
985a71d1
...
@@ -565,6 +565,7 @@
...
@@ -565,6 +565,7 @@
#define CONFIG_SYS_GPIO_PHY1_RST 12
#define CONFIG_SYS_GPIO_PHY1_RST 12
#define CONFIG_SYS_GPIO_FLASH_WP 14
#define CONFIG_SYS_GPIO_FLASH_WP 14
#define CONFIG_SYS_GPIO_PHY0_RST 22
#define CONFIG_SYS_GPIO_PHY0_RST 22
#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
#define CONFIG_SYS_GPIO_DSPIC_READY 51
#define CONFIG_SYS_GPIO_DSPIC_READY 51
#define CONFIG_SYS_GPIO_CAN_ENABLE 53
#define CONFIG_SYS_GPIO_CAN_ENABLE 53
#define CONFIG_SYS_GPIO_LSB_ENABLE 54
#define CONFIG_SYS_GPIO_LSB_ENABLE 54
...
@@ -577,6 +578,13 @@
...
@@ -577,6 +578,13 @@
#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
#define CONFIG_SYS_GPIO_WATCHDOG 63
#define CONFIG_SYS_GPIO_WATCHDOG 63
/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
#ifdef CONFIG_LCD4_LWMON5
#define GPIO49_VAL 0
#else
#define GPIO49_VAL 1
#endif
/*
/*
* PPC440 GPIO Configuration
* PPC440 GPIO Configuration
*/
*/
...
@@ -635,7 +643,7 @@
...
@@ -635,7 +643,7 @@
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0},
/* GPIO46 UIC_IRQ(7) DMA_REQ(0) */
\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0},
/* GPIO46 UIC_IRQ(7) DMA_REQ(0) */
\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0},
/* GPIO47 UIC_IRQ(8) DMA_ACK(0) */
\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0},
/* GPIO47 UIC_IRQ(8) DMA_ACK(0) */
\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0},
/* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */
\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0},
/* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */
\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO
_OUT_1
},
/* GPIO49 Unselect via TraceSelect Bit */
\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO
49_VAL
},
/* GPIO49 Unselect via TraceSelect Bit */
\
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0},
/* GPIO50 Unselect via TraceSelect Bit */
\
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0},
/* GPIO50 Unselect via TraceSelect Bit */
\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0},
/* GPIO51 Unselect via TraceSelect Bit */
\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0},
/* GPIO51 Unselect via TraceSelect Bit */
\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0},
/* GPIO52 Unselect via TraceSelect Bit */
\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0},
/* GPIO52 Unselect via TraceSelect Bit */
\
...
...
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