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Commit 97c02d87 authored by Thierry Reding's avatar Thierry Reding Committed by Tom Warren
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ARM: tegra: clk_m is the architected timer source clock


While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies. clk_m will be divided down
from the oscillator.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
parent c043c025
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...@@ -679,8 +679,8 @@ void arch_timer_init(void) ...@@ -679,8 +679,8 @@ void arch_timer_init(void)
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val; u32 freq, val;
freq = clock_get_rate(CLOCK_ID_OSC); freq = clock_get_rate(CLOCK_ID_CLK_M);
debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
/* ARM CNTFRQ */ /* ARM CNTFRQ */
asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
......
...@@ -859,8 +859,8 @@ void arch_timer_init(void) ...@@ -859,8 +859,8 @@ void arch_timer_init(void)
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val; u32 freq, val;
freq = clock_get_rate(CLOCK_ID_OSC); freq = clock_get_rate(CLOCK_ID_CLK_M);
debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
/* ARM CNTFRQ */ /* ARM CNTFRQ */
asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
......
...@@ -1014,13 +1014,11 @@ void arch_timer_init(void) ...@@ -1014,13 +1014,11 @@ void arch_timer_init(void)
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val; u32 freq, val;
freq = clock_get_rate(CLOCK_ID_OSC); freq = clock_get_rate(CLOCK_ID_CLK_M);
debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
/* ARM CNTFRQ */ if (current_el() == 3)
#ifndef CONFIG_ARM64 asm("msr cntfrq_el0, %0\n" : : "r" (freq));
asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
#endif
/* Only Tegra114+ has the System Counter regs */ /* Only Tegra114+ has the System Counter regs */
debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
......
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