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Commit 9757b65b authored by Peter Crosthwaite's avatar Peter Crosthwaite Committed by Michal Simek
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arm: dts: zynq: Add digilent ZYBO board dts


It's a Zynq board similar in design to the currently supported ones.
512MB of RAM and UART1 is used.

Signed-off-by: default avatarPeter Crosthwaite <crosthwaite.peter@gmail.com>
Acked-by: default avatarJagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 290f1f99
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...@@ -34,6 +34,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ ...@@ -34,6 +34,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \ zynq-zc706.dtb \
zynq-zed.dtb \ zynq-zed.dtb \
zynq-zybo.dtb \
zynq-microzed.dtb \ zynq-microzed.dtb \
zynq-zc770-xm010.dtb \ zynq-zc770-xm010.dtb \
zynq-zc770-xm012.dtb \ zynq-zc770-xm012.dtb \
......
/*
* Digilent ZYBO board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZYBO Board";
compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000";
aliases {
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x20000000>;
};
};
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