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Commit 97405d84 authored by Lokesh Vutla's avatar Lokesh Vutla Committed by Tom Rini
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ARM: DRA7xx: clocks: Update PLL values 


Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: default avatarSricharan R <r.sricharan@ti.com>
parent 7f36c88f
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