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Commit 95a40e39 authored by Troy Kisky's avatar Troy Kisky
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nitrogem8m: remove ddr, mv ddr/lpddr4_timing.c up

parent 731039c7
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...@@ -9,5 +9,4 @@ obj-y += nitrogen8m.o mmc.o ...@@ -9,5 +9,4 @@ obj-y += nitrogen8m.o mmc.o
ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_BUILD
obj-y += spl.o obj-y += spl.o
obj-y += lpddr4_timing.o obj-y += lpddr4_timing.o
obj-y += ddr/lpddr4_timing.o
endif endif
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
void ddr_init1(struct dram_timing_info *dram_timing);
extern struct dram_timing_info lpddr4_timing_;
void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num);
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...@@ -23,14 +23,13 @@ ...@@ -23,14 +23,13 @@
#ifdef CONFIG_IMX8M_LPDDR4 #ifdef CONFIG_IMX8M_LPDDR4
#include <asm/arch/imx8m_ddr.h> #include <asm/arch/imx8m_ddr.h>
#endif #endif
#include "ddr/ddr.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
void spl_dram_init(void) void spl_dram_init(void)
{ {
/* ddr init */ /* ddr init */
ddr_init(&lpddr4_timing_); ddr_init(&lpddr4_timing);
} }
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
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