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Commit 8ff3de61 authored by Kumar Gala's avatar Kumar Gala
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Handle MPC85xx PCIe reset errata (PCI-Ex 38)


On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 82ac8c97
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...@@ -112,6 +112,29 @@ fsl_pci_init(struct pci_controller *hose) ...@@ -112,6 +112,29 @@ fsl_pci_init(struct pci_controller *hose)
pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
enabled = ltssm >= PCI_LTSSM_L0; enabled = ltssm >= PCI_LTSSM_L0;
#ifdef CONFIG_FSL_PCIE_RESET
if (ltssm == 1) {
int i;
debug("....PCIe link error. "
"LTSSM=0x%02x.", ltssm);
pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
temp32 = pci->pdb_stat;
udelay(100);
debug(" Asserting PCIe reset @%x = %x\n",
&pci->pdb_stat, pci->pdb_stat);
pci->pdb_stat &= ~0x08000000; /* clear reset */
asm("sync;isync");
for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM,
&ltssm);
udelay(1000);
debug("....PCIe link error. "
"LTSSM=0x%02x.\n", ltssm);
}
enabled = ltssm >= PCI_LTSSM_L0;
}
#endif
if (!enabled) { if (!enabled) {
debug("....PCIE link error. Skipping scan." debug("....PCIE link error. Skipping scan."
"LTSSM=0x%02x\n", ltssm); "LTSSM=0x%02x\n", ltssm);
......
...@@ -144,7 +144,9 @@ typedef struct ccsr_pci { ...@@ -144,7 +144,9 @@ typedef struct ccsr_pci {
u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
char res23[456]; /* (- #x1000 #xe38) 456 */ char res23[200];
u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
char res24[252];
} ccsr_fsl_pci_t; } ccsr_fsl_pci_t;
#endif /*__IMMAP_fsl_pci__*/ #endif /*__IMMAP_fsl_pci__*/
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
......
...@@ -42,6 +42,7 @@ ...@@ -42,6 +42,7 @@
#undef CONFIG_RIO #undef CONFIG_RIO
#undef CONFIG_PCI2 #undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
......
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
#define CONFIG_PCI1 1 /* PCI controller */ #define CONFIG_PCI1 1 /* PCI controller */
#define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */ #define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
......
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