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Commit 8e99ecd7 authored by Benoît Thébaudeau's avatar Benoît Thébaudeau Committed by Albert ARIBAUD
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mxc: Define architecture identifier


Define ARCH_MXC for i.MX devices. This is useful to identify features or
behaviors common to all i.MX SoCs.

The i.MX28 is omitted because its architecture is a bit different (like imx/mxc
vs. mxs in Linux).

Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
parent ac966aac
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#ifndef _IMX_REGS_H
#define _IMX_REGS_H
#define ARCH_MXC
/* ------------------------------------------------------------------------
* Motorola IMX system registers
* ------------------------------------------------------------------------
......
......@@ -172,6 +172,8 @@ struct aips_regs {
#endif
#define ARCH_MXC
/* AIPS 1 */
#define IMX_AIPS1_BASE (0x43F00000)
#define IMX_MAX_BASE (0x43F04000)
......
......@@ -196,6 +196,8 @@ struct fuse_bank0_regs {
#endif
#define ARCH_MXC
#define IMX_IO_BASE 0x10000000
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
......
......@@ -541,6 +541,8 @@ struct esdc_regs {
#endif
#define ARCH_MXC
#define __REG(x) (*((volatile u32 *)(x)))
#define __REG16(x) (*((volatile u16 *)(x)))
#define __REG8(x) (*((volatile u8 *)(x)))
......
......@@ -25,6 +25,8 @@
#ifndef __ASM_ARCH_MX35_H
#define __ASM_ARCH_MX35_H
#define ARCH_MXC
/*
* IRAM
*/
......
......@@ -23,6 +23,8 @@
#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
#define __ASM_ARCH_MX5_IMX_REGS_H__
#define ARCH_MXC
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_SOC_BASE_ADDR 0x40000000
......
......@@ -19,6 +19,8 @@
#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
#define __ASM_ARCH_MX6_IMX_REGS_H__
#define ARCH_MXC
#define CONFIG_SYS_CACHELINE_SIZE 32
#define ROMCP_ARB_BASE_ADDR 0x00000000
......
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