imx8m: add is_imx8mq/is_imx8mm

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

arch/arm/include/asm/arch-imx/cpu.h

@@ -24,13 +24,14 @@
 #define MXC_CPU_MX6QP		0x69
 #define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
-#define MXC_CPU_IMX8MQ		0x82
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
+#define MXC_CPU_IMX8MQ		0x82
+#define MXC_CPU_IMX8MM		0x83 /* 0x83 is dummy value */
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
-#define MXC_SOC_IMX8M		0x80
+
 #define MXC_SOC_MX7ULP		0xE0 /* dummy */
 
 #define CHIP_REV_1_0            0x10

arch/arm/include/asm/mach-imx/sys_proto.h

@@ -26,7 +26,6 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
-#define is_mx8m() (is_soc_type(MXC_SOC_IMX8M))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
@@ -41,6 +40,10 @@
 
 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
 
+#define is_imx8m() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MM))
+#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
+#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM))
+
 #ifdef CONFIG_MX6
 #define IMX6_SRC_GPR10_BMODE		BIT(28)
 

arch/arm/mach-imx/cpu.c

@@ -157,8 +157,10 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_IMX8MM:
+		return "8MM";   /* Quad-core version of the imx8mm */
 	case MXC_CPU_IMX8MQ:
-		return "8MQ";	/* Quad-core version of the imx8m */
+		return "8MQ";   /* Quad-core version of the imx8mq */
 	case MXC_CPU_MX7S:
 		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:

arch/arm/mach-imx/imx8m/soc.c

@@ -135,20 +135,33 @@ u32 get_cpu_rev(void)
 	struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&ana_pll->digprog);
 	u32 type = (reg >> 16) & 0xff;
+	u32 major_low = (reg >> 8) & 0xff;
 	u32 rom_version;
 
 	reg &= 0xff;
 
+	/* iMX8MM */
+	if (major_low == 0x41)
+		return ((type + 1) << 12) | reg;
+	/* iMX8MQ */
 	if (reg == CHIP_REV_1_0) {
 		/*
 		 * For B0 chip, the DIGPROG is not updated, still TO1.0.
-		 * we have to check ROM version further
+		 * we have to check ROM version or OCOTP_READ_FUSE_DATA
 		 */
-		rom_version = readl((void __iomem *)ROM_VERSION_A0);
-		if (rom_version != CHIP_REV_1_0) {
-			rom_version = readl((void __iomem *)ROM_VERSION_B0);
-			if (rom_version >= CHIP_REV_2_0)
-				reg = CHIP_REV_2_0;
+		if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40))
+				== 0xff0055aa) {
+			/* 0xff0055aa is magic number for B1 */
+			reg = 0x21;
+		} else {
+#define ROM_VERSION_A0		0x800
+#define ROM_VERSION_B0		0x83C
+			rom_version = readl((void __iomem *)ROM_VERSION_A0);
+			if (rom_version != CHIP_REV_1_0) {
+				rom_version = readl((void __iomem *)ROM_VERSION_B0);
+				if (rom_version >= CHIP_REV_2_0)
+					reg = CHIP_REV_2_0;
+			}
 		}
 	}
 

drivers/net/fec_mxc.c

@@ -564,7 +564,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
 	writel(0x00000000, &fec->eth->gaddr2);
 
 	/* Do not access reserved register */
-	if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
+	if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) {
 		/* clear MIB RAM */
 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
 			writel(0, i);