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Commit 8aecbcd1 authored by Ken Ma's avatar Ken Ma Committed by Stefan Roese
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arm64: a37xx: dts: Fix the number of GPIO on south bridge

The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43286


Reviewed-by: default avatarHua Jing <jinghua@marvell.com>
Tested-by: default avatariSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: default avatarKen Ma <make@marvell.com>
Signed-off-by: default avatarStefan Roese <sr@denx.de>
parent 44ac747b
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...@@ -168,7 +168,7 @@ ...@@ -168,7 +168,7 @@
reg = <0x18800 0x100>, <0x18C00 0x20>; reg = <0x18800 0x100>, <0x18C00 0x20>;
gpiosb: gpiosb { gpiosb: gpiosb {
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-ranges = <&pinctrl_sb 0 0 29>; gpio-ranges = <&pinctrl_sb 0 0 30>;
gpio-controller; gpio-controller;
interrupts = interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
......
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