Coding style cleanup; update CHANEGLOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

+commit 7c803be2eb3cae245dedda438776e08fb122250f
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 16 18:02:19 2008 +0200
+
+    TQM8xx: Fix CFI flash driver support for all TQM8xx based boards
+
+    After switching to using the CFI flash driver, the correct remapping
+    of the flash banks was forgotten.
+
+    Also, some boards were not adapted, and the old legacy flash driver
+    was not removed yet.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c0d2f87d6c450128b88e73eea715fa3654f65b6c
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Sep 14 00:59:35 2008 +0200
+
+    Prepare v2008.10-rc2
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f12e4549b6fb01cd2654348af95a3c7a6ac161e7
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Sep 13 02:23:05 2008 +0200
+
+    Coding style cleanup, update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 0c32565f536609d78feef35c88bbc39d3ac53a73
 Author: Peter Tyser <ptyser@xes-inc.com>
 Date:	Wed Sep 10 09:18:34 2008 -0500

board/tqc/tqm8xx/tqm8xx.c

@@ -400,8 +400,6 @@ phys_size_t initdram (int board_type)
 	memctl->memc_or5 = CFG_OR5_ISP1362;
 	memctl->memc_br5 = CFG_BR5_ISP1362;
 #endif							/* CONFIG_ISP1362_USB */
-
-
 	return (size_b0 + size_b1);
 }
 
@@ -463,8 +461,9 @@ int misc_init_r (void)
 	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
 		trlx = OR_TRLX;
 		scy *= 2;
-	} else
+	} else {
 		trlx = 0;
+	}
 
 	/*
 	 * We assume that each 10MHz of bus clock require 1-clk SCY
@@ -501,9 +500,11 @@ int misc_init_r (void)
 	flash_or_timing = (scy << 4) | trlx |
 		(CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
 
-	memctl->memc_or0 = flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
+	memctl->memc_or0 =
+		flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
 #else
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
+	memctl->memc_or0 =
+		CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
 #endif
 	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
@@ -518,8 +519,10 @@ int misc_init_r (void)
 		memctl->memc_or1 = CFG_OR_TIMING_FLASH |
 			(-flash_info[1].size & 0xFFFF8000);
 #endif
-		memctl->memc_br1 = ((CFG_FLASH_BASE + flash_info[0].size) & BR_BA_MSK) |
-				    BR_MS_GPCM | BR_V;
+		memctl->memc_br1 =
+			((CFG_FLASH_BASE +
+			  flash_info[0].
+			  size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
 		       memctl->memc_br1, memctl->memc_or1);
@@ -609,7 +612,4 @@ int last_stage_init(void)
 
 	return 0;
 }
-
 #endif
-
-/* ------------------------------------------------------------------------- */