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Commit 84aa7fc8 authored by Troy Kisky's avatar Troy Kisky
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nitrogen8mm: initial addition 


Signed-off-by: default avatarTroy Kisky <troy.kisky@boundarydevices.com>
parent bfb66bb7
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arch/arm/dts/imx8mm-nitrogen8mm.dts 0 → 100644
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View file @ 84aa7fc8
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "fsl-imx8mm.dtsi"
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
iomuxc_pinctrl: iomuxc-pinctrlgrp {
};
};
&iomuxc_pinctrl {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_1: i2c1_1grp {
fsl,pins = <
#define GP_I2C1_SCL <&gpio5 14 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
#define GP_I2C1_SDA <&gpio5 15 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_1: i2c2_1grp {
fsl,pins = <
#define GP_I2C2_SCL <&gpio5 16 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
#define GP_I2C2_SDA <&gpio5 17 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_1: i2c3_1grp {
fsl,pins = <
#define GP_I2C3_SCL <&gpio5 18 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
#define GP_I2C3_SDA <&gpio5 19 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c4_1: i2c4_1grp {
fsl,pins = <
#define GP_I2C4_SCL <&gpio5 20 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
#define GP_I2C4_SDA <&gpio5 21 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_reg_usdhc2_vqmmc: reg_usdhc2_vqmmcgrp {
fsl,pins = <
#define GP_USDHC2_VSEL <&gpio3 2 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x16
>;
};
pinctrl_uart2: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x16
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
>;
};
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x16
MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x16
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
#define GP_EMMC_RESET <&gpio2 10 GPIO_ACTIVE_LOW>
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
#define GP_USDHC2_CD <&gpio2 12 GPIO_ACTIVE_LOW>
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
/* Bluetooth slow clock */
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
/ {
model = "Boundary nitrogen8mm(mini) board";
compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm-evk", "fsl,imx8mm";
chosen {
bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
stdout-patch = &uart2;
};
reg_usdhc2_vqmmc: regulator-usdhc2 {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
regulator-name = "reg_sd2_vsel";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-type = "voltage";
regulator-boot-on;
regulator-always-on;
gpios = GP_USDHC2_VSEL;
states = <1800000 0x1
3300000 0x0>;
};
reg_vref_1v8: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vref_3v3: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_1>;
scl-gpios = GP_I2C1_SCL;
sda-gpios = GP_I2C1_SDA;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_1>;
scl-gpios = GP_I2C2_SCL;
sda-gpios = GP_I2C2_SDA;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_1>;
scl-gpios = GP_I2C3_SCL;
sda-gpios = GP_I2C3_SDA;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_1>;
scl-gpios = GP_I2C4_SCL;
sda-gpios = GP_I2C4_SDA;
status = "okay";
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
#if 0
at803x,led-act-blind-workaround;
at803x,eee-okay;
at803x,vddio-1p8v;
#endif
};
};
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
power-polarity-active-high;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
power-polarity-active-high;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
bus-width = <8>;
no-mmc-hs400;
#if 0
pinctrl-names = "default", "state_100mhz", "state_200mhz";
#else
pinctrl-names = "default";
#endif
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
reset-gpios = GP_EMMC_RESET;
non-removable;
vqmmc-1-8-v;
vmmc-supply = <&reg_vref_3v3>;
#if 0
vqmmc-supply = <&reg_vref_1v8>;
#endif
status = "okay";
};
&usdhc2 {
bus-width = <4>;
cd-gpios = GP_USDHC2_CD;
#if 1
pinctrl-names = "default", "state_100mhz", "state_200mhz";
#else
pinctrl-names = "default";
#endif
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vqmmc-supply = <&reg_usdhc2_vqmmc>;
status = "okay";
};
&usdhc3 {
#if 0
pinctrl-names = "default", "state_100mhz", "state_200mhz";
#else
pinctrl-names = "default";
#endif
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <4>;
non-removable;
status = "disabled";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
arch/arm/mach-imx/imx8m/Kconfig
+ 6
− 0
View file @ 84aa7fc8
......@@ -26,6 +26,11 @@ config TARGET_NITROGEN8M_SOM
select IMX8MQ
select SUPPORT_SPL
config TARGET_NITROGEN8MM
bool "nitrogen8mm"
select IMX8MM
select SUPPORT_SPL
config TARGET_IMX8MM_EVK
bool "imx8mm_evk"
select IMX8MM
......@@ -38,5 +43,6 @@ config SYS_SOC
source "board/boundary/nitrogen8m/Kconfig"
source "board/boundary/nitrogen8m_som/Kconfig"
source "board/boundary/nitrogen8mm/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
endif
board/boundary/common/padctrl-imx8mm.h
+ 1
− 1
View file @ 84aa7fc8
......@@ -20,4 +20,4 @@
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
board/boundary/nitrogen8mm/Kconfig 0 → 100644
+ 14
− 0
View file @ 84aa7fc8
if TARGET_NITROGEN8MM
config SYS_BOARD
default "nitrogen8mm"
config SYS_VENDOR
default "boundary"
config SYS_CONFIG_NAME
default "nitrogen8mm"
source "board/boundary/common/Kconfig"
endif
board/boundary/nitrogen8mm/Makefile 0 → 100644
+ 12
− 0
View file @ 84aa7fc8
#
# Copyright 2018 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += nitrogen8mm.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += lpddr4_timing.o
endif
board/boundary/nitrogen8mm/lpddr4_timing.c 0 → 100644
+ 1272
− 0
View file @ 84aa7fc8
This diff is collapsed.
board/boundary/nitrogen8mm/nitrogen8mm.c 0 → 100644
+ 161
− 0
View file @ 84aa7fc8
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/fbpanel.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <spl.h>
#include <asm/mach-imx/dma.h>
#include <usb.h>
#include <asm/mach-imx/video.h>
#include "../common/padctrl.h"
#include "../common/bd_common.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
static iomux_v3_cfg_t const init_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
#define GP_I2C2_SN65DSI83_EN IMX_GPIO_NR(1, 9)
IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 | MUX_PAD_CTRL(0x26),
IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(PAD_CTL_DSE1 | PAD_CTL_ODE),
#ifdef CONFIG_FEC_MXC
/* PHY - AR8035 */
IMX8MM_PAD_ENET_MDIO_ENET1_MDIO | MUX_PAD_CTRL(PAD_CTRL_ENET_MDC),
IMX8MM_PAD_ENET_MDC_ENET1_MDC | MUX_PAD_CTRL(PAD_CTRL_ENET_MDIO),
IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(PAD_CTRL_ENET_TX),
IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 | MUX_PAD_CTRL(PAD_CTRL_ENET_TX),
IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 | MUX_PAD_CTRL(PAD_CTRL_ENET_TX),
IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 | MUX_PAD_CTRL(PAD_CTRL_ENET_TX),
IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 | MUX_PAD_CTRL(PAD_CTRL_ENET_TX),
IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC | MUX_PAD_CTRL(PAD_CTRL_ENET_TX),
#endif
#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 | MUX_PAD_CTRL(0x41),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
gpio_request(GP_I2C2_SN65DSI83_EN, "sn65en");
gpio_direction_output(GP_I2C2_SN65DSI83_EN, 0);
imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
gpio_direction_output(GP_EMMC_RESET, 1);
set_wdog_reset(wdog);
return 0;
}
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
/* TODO */
return 0;
}
#endif
int dram_init(void)
{
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
else
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
return 0;
}
#endif
int board_init(void)
{
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
#ifdef CONFIG_FSL_FSPI
board_qspi_init();
#endif
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand(); /* SPL will call the board_early_init_f */
#endif
return 0;
}
static void set_env_vars(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (!env_get("board"))
env_set("board", "nitrogen8mm");
env_set("soc", "imx8mm");
env_set("imx_cpu", get_imx_type((get_cpu_rev() & 0xFF000) >> 12));
env_set("uboot_defconfig", CONFIG_DEFCONFIG);
#endif
}
void board_set_default_env(void)
{
set_env_vars();
#ifdef CONFIG_CMD_FBPANEL
fbp_setup_env_cmds();
#endif
board_eth_addresses();
}
int board_usb_init(int index, enum usb_init_type init)
{
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
imx8m_usb_power(index, false);
return 0;
}
int board_late_init(void)
{
set_env_vars();
#ifdef CONFIG_ENV_IS_IN_MMC
env_set_ulong("mmcdev", 0);
run_command("mmc dev 0", 0);
#endif
return 0;
}
#ifdef CONFIG_FSL_FASTBOOT
#ifdef CONFIG_ANDROID_RECOVERY
int is_recovery_key_pressing(void)
{
return 0; /*TODO*/
}
#endif /*CONFIG_ANDROID_RECOVERY*/
#endif /*CONFIG_FSL_FASTBOOT*/
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/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
#include <malloc.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8m_ddr.h>
DECLARE_GLOBAL_DATA_PTR;
void spl_dram_init(void)
{
/* ddr train */
ddr_init(&lpddr4_timing);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE3 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1[] = {
{
.scl = {
.i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
.gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
.gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
},
{
.scl = {
.i2c_mode = IMX8MM_PAD_I2C2_SCL_I2C2_SCL | PC,
.gpio_mode = IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 | PC,
.gp = IMX_GPIO_NR(5, 16),
},
.sda = {
.i2c_mode = IMX8MM_PAD_I2C2_SDA_I2C2_SDA | PC,
.gpio_mode = IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 | PC,
.gp = IMX_GPIO_NR(5, 17),
},
},
{
.scl = {
.i2c_mode = IMX8MM_PAD_I2C3_SCL_I2C3_SCL | PC,
.gpio_mode = IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 | PC,
.gp = IMX_GPIO_NR(5, 18),
},
.sda = {
.i2c_mode = IMX8MM_PAD_I2C3_SDA_I2C3_SDA | PC,
.gpio_mode = IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 | PC,
.gp = IMX_GPIO_NR(5, 19),
},
},
{
.scl = {
.i2c_mode = IMX8MM_PAD_I2C4_SCL_I2C4_SCL | PC,
.gpio_mode = IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 | PC,
.gp = IMX_GPIO_NR(5, 20),
},
.sda = {
.i2c_mode = IMX8MM_PAD_I2C4_SDA_I2C4_SDA | PC,
.gpio_mode = IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 | PC,
.gp = IMX_GPIO_NR(5, 21),
},
},
};
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MM_PAD_SD1_CLK_USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_CMD_USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 | MUX_PAD_CTRL(0x41),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
#define GP_USDHC2_VSEL IMX_GPIO_NR(3, 2)
IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 | MUX_PAD_CTRL(0x16),
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 8, .gp_reset = GP_EMMC_RESET},
{.esdhc_base = USDHC2_BASE_ADDR, .bus_width = 4,},
};
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_request(GP_EMMC_RESET, "emmc_reset");
gpio_direction_output(GP_EMMC_RESET, 0);
udelay(500);
gpio_direction_output(GP_EMMC_RESET, 1);
break;
case 1:
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
gpio_direction_input(USDHC2_CD_GPIO);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
return 1;
case USDHC2_BASE_ADDR:
ret = gpio_get_value(USDHC2_CD_GPIO);
return ret ? 0 : 1;
}
printf("c\n");
return 0;
}
int power_init_boundary(void)
{
int ret;
unsigned char buf[4];
i2c_set_bus_num(0);
#define PF8100 0x08
#define SW2_VOLT 0x59
#define SW3_VOLT 0x61
#define SW4_VOLT 0x69
#define SW5_VOLT 0x71
buf[0] = 0x50; /* (.90-.4)*160=.50*160=80=0x50 80/160+.4=.90 gpu/dram/arm */
ret = i2c_write(PF8100, SW2_VOLT, 1, buf, 1);
if (ret)
return ret;
ret = i2c_write(PF8100, SW4_VOLT, 1, buf, 1);
if (ret)
return ret;
ret = i2c_write(PF8100, SW3_VOLT, 1, buf, 1);
if (ret)
return ret;
buf[0] = 0x40; /* (.80-.4)*160=.40*160=64=0x40 64/160+.4=.80 vpu */
ret = i2c_write(PF8100, SW5_VOLT, 1, buf, 1);
gpio_request(GP_USDHC2_VSEL, "usdhc2_vsel");
gpio_direction_output(GP_USDHC2_VSEL, 0);
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
return ret;
}
void spl_board_init(void)
{
int i;
enable_tzc380();
for (i = 0; i < ARRAY_SIZE(i2c_pad_info1); i++)
setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1[i]);
malloc(sizeof(int));
power_init_boundary();
/* DDR initialization */
spl_dram_init();
#ifndef CONFIG_SPL_USB_SDP_SUPPORT
/* Serial download mode */
if (is_usb_boot()) {
puts("Back to ROM, SDP\n");
restore_boot_params();
}
#endif
puts("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
configs/nitrogen8mm_2g_defconfig 0 → 100644
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CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_NITROGEN8MM=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x30860000
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-nitrogen8mm"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000,DDR_MB=2048,DEFCONFIG=\"nitrogen8mm_2g\""
CONFIG_BOOTSTAGE_STASH_SIZE=4096
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_IMLS=y
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_FSL_SEC_LE=y
CONFIG_IMX8M_LPDDR4=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DEBUG_UART_MXC=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Boundary"
CONFIG_USB_GADGET_VENDOR_NUM=0x3016
CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_DEVADDR="00:19:b8:00:00:02"
CONFIG_USBNET_HOST_ADDR="00:19:b8:00:00:01"
CONFIG_USB_HOST_ETHER=y
include/configs/nitrogen8mm.h 0 → 100644
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/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __NITROGEN8MM_H
#define __NITROGEN8MM_H
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
#endif
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x91fff0
#define CONFIG_SPL_BSS_START_ADDR 0x00910000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x00911000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
#undef CONFIG_BLK
#undef CONFIG_DM_MMC
#undef CONFIG_DM_PMIC
#undef CONFIG_DM_PMIC_PFUZE100
#define CONFIG_SYS_I2C
#endif
#define CONFIG_CMD_READ
#define CONFIG_FASTBOOT_USB_DEV 0
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_BOARD_LATE_INIT
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 4
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
#endif
/* Link Definitions */
#define CONFIG_LOADADDR 0x40480000
#define CONFIG_SYS_TEXT_BASE 0x40200000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 0x2000
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 1 /* mmcblk0boot0 */
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
#define CONFIG_BAUDRATE 115200
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_MXC_OCOTP
#define CONFIG_CMD_FUSE
#define CONFIG_IMX_BOOTAUX
/* USDHC */
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_OCOTP
#define CONFIG_CMD_FUSE
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#endif
#define CONFIG_SYS_I2C_SPEED 100000
/* USB configs */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_MASS_STORAGE
#endif
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_OF_SYSTEM_SETUP
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_VIDEO_SKIP
#endif
#ifndef BD_CONSOLE
#if CONFIG_MXC_UART_BASE == UART2_BASE_ADDR
#define BD_CONSOLE "ttymxc1"
#elif CONFIG_MXC_UART_BASE == UART1_BASE_ADDR
#define BD_CONSOLE "ttymxc0"
#endif
#endif
#ifdef CONFIG_CMD_MMC
#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 1) func(MMC, mmc, 0)
#else
#define DISTRO_BOOT_DEV_MMC(func)
#endif
#if 0
#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
#else
#define DISTRO_BOOT_DEV_USB(func)
#endif
#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
DISTRO_BOOT_DEV_MMC(func) \
DISTRO_BOOT_DEV_USB(func)
#endif
#include <config_distro_bootcmd.h>
#define CONFIG_CMD_FBPANEL
#define BD_RAM_BASE 0x80000000
#define BD_RAM_SCRIPT "40008000"
#define BD_RAM_KERNEL "40800000"
#define BD_RAM_RAMDISK "42800000"
#define BD_RAM_FDT "43000000"
/* M4 specific */
#define SYS_AUXCORE_BOOTDATA_DDR 0x80000000
#define SYS_AUXCORE_BOOTDATA_TCM 0x007E0000
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=" BD_CONSOLE "\0" \
"env_dev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"env_part=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"m4boot=load ${devtype} ${devnum}:1 ${m4loadaddr} ${m4image}; " \
"dcache flush; bootaux ${m4loadaddr}\0" \
"m4image=m4_fw.bin\0" \
"m4loadaddr="__stringify(SYS_AUXCORE_BOOTDATA_TCM)"\0" \
"netargs=setenv bootargs console=${console},115200 root=/dev/nfs rw " \
"ip=dhcp nfsroot=${tftpserverip}:${nfsroot},v3,tcp\0" \
"netboot=run netargs; " \
"if test -z \"${fdt_file}\" -a -n \"${soc}\"; then " \
"setenv fdt_file ${soc}-${board}${boardver}.dtb; " \
"fi; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${loadaddr} ${tftpserverip}:Image; " \
"if ${get_cmd} ${fdt_addr} ${tftpserverip}:${fdt_file}; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi;\0" \
"net_upgradeu=dhcp " BD_RAM_SCRIPT " net_upgradeu.scr && source " BD_RAM_SCRIPT "\0" \
"otg_upgradeu=run usbnetwork; tftp " BD_RAM_SCRIPT " net_upgradeu.scr && source " BD_RAM_SCRIPT "\0" \
"upgradeu=setenv boot_scripts upgrade.scr; boot;" \
"echo Upgrade failed!; setenv boot_scripts boot.scr\0" \
"usbnet_devaddr=00:19:b8:00:00:02\0" \
"usbnet_hostaddr=00:19:b8:00:00:01\0" \
"usbnetwork=setenv ethact usb_ether; " \
"setenv ipaddr 10.0.0.2; " \
"setenv netmask 255.255.255.0; " \
"setenv serverip 10.0.0.1;\0" \
BOOTENV
/*
* PCI express
*/
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#endif
#endif
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