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Commit 7a22cd53 authored by Wolfgang Denk's avatar Wolfgang Denk
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Fix au1x00_serial baud rate calculation:

remove hardcoded cpu clock divisor and use register instead;
round up instead of truncate
Patch by Andrew Dyer, 15 Feb 2005
parent 875c7893
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...@@ -2,8 +2,13 @@ ...@@ -2,8 +2,13 @@
Changes for U-Boot 1.1.4: Changes for U-Boot 1.1.4:
====================================================================== ======================================================================
* Fix au1x00_serial baud rate calculation:
remove hardcoded cpu clock divisor and use register instead;
round up instead of truncate
Patch by Andrew Dyer, 15 Feb 2005
* Add Xilinx Spartan3 family FPGA support * Add Xilinx Spartan3 family FPGA support
Patch by Kurt Stremerch, 14 February 2005 Patch by Kurt Stremerch, 14 Feb 2005
* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET * Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET
Patch by Zachary Landau, 11 Feb 2005 Patch by Zachary Landau, 11 Feb 2005
......
...@@ -70,9 +70,21 @@ void serial_setbrg (void) ...@@ -70,9 +70,21 @@ void serial_setbrg (void)
{ {
volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK); volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR); volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
int sd;
int divisorx2;
/* Set baudrate - FIXME for bus speeds != CPU/2 */ /* sd is system clock divisor */
*uart_clk = ((CFG_HZ/(CONFIG_BAUDRATE * 64))); /* see section 10.4.5 in au1550 datasheet */
sd = (*sys_powerctrl & 0x03) + 2;
/* calulate 2x baudrate and round */
divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE)));
if (divisorx2 & 0x01)
divisorx2 = divisorx2 + 1;
*uart_clk = divisorx2 / 2;
/* Set parity, stop bits and word length to 8N1 */ /* Set parity, stop bits and word length to 8N1 */
*uart_lcr = UART_LCR_WLEN8; *uart_lcr = UART_LCR_WLEN8;
......
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