board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config

The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

board/freescale/b4860qds/b4_pbi.cfg

@@ -22,6 +22,9 @@
 09110024 00100008
 09110028 00100008
 0911002c 00100008
+#slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
 #Flush PBL data
 09138000 00000000
 091380c0 00000000