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Commit 672a45e8 authored by Tom Rini's avatar Tom Rini
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Merge branch 'master' of http://git.denx.de/u-boot-sunxi

parents b1033500 1a83fb4a
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...@@ -222,7 +222,12 @@ struct sunxi_ccm_reg { ...@@ -222,7 +222,12 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31) #define CCM_PLL11_CTRL_EN (0x1 << 31)
#if defined(CONFIG_MACH_SUN50I)
/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
#else
#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
#endif
#define AXI_GATE_OFFSET_DRAM 0 #define AXI_GATE_OFFSET_DRAM 0
......
...@@ -2,6 +2,7 @@ CONFIG_ARM=y ...@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120 CONFIG_DRAM_ZQ=120
CONFIG_INITIAL_USB_SCAN_DELAY=2000
CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN="" CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
......
...@@ -11,3 +11,5 @@ CONFIG_SPL=y ...@@ -11,3 +11,5 @@ CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set # CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set # CONFIG_CMD_FPGA is not set
CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD=y
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
...@@ -340,9 +340,16 @@ int musb_usb_probe(struct udevice *dev) ...@@ -340,9 +340,16 @@ int musb_usb_probe(struct udevice *dev)
int musb_usb_remove(struct udevice *dev) int musb_usb_remove(struct udevice *dev)
{ {
struct musb_host_data *host = dev_get_priv(dev); struct musb_host_data *host = dev_get_priv(dev);
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
musb_stop(host->host); musb_stop(host->host);
sunxi_usb_phy_exit(0);
#ifdef CONFIG_SUNXI_GEN_SUN6I
clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
#endif
clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
return 0; return 0;
} }
......
...@@ -100,7 +100,7 @@ ...@@ -100,7 +100,7 @@
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000. * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
*/ */
#define CONFIG_SYS_INIT_RAM_ADDR 0x10000 #define CONFIG_SYS_INIT_RAM_ADDR 0x10000
#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ #define CONFIG_SYS_INIT_RAM_SIZE 0xA000 /* 40 KiB */
#else #else
#define CONFIG_SYS_INIT_RAM_ADDR 0x0 #define CONFIG_SYS_INIT_RAM_ADDR 0x0
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
...@@ -213,8 +213,7 @@ ...@@ -213,8 +213,7 @@
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) #if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
/* FIXME: 40 KiB instead of 32 KiB ? */ #define LOW_LEVEL_SRAM_STACK 0x0001A000
#define LOW_LEVEL_SRAM_STACK 0x00018000
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#else #else
/* end of 32 KiB in sram */ /* end of 32 KiB in sram */
......
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