Merge branch 'master' of git://git.denx.de/u-boot-mips

Kconfig

@@ -268,7 +268,7 @@ config SYS_EXTRA_OPTIONS
 
 config SYS_TEXT_BASE
 	depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
-		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE
+		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS
 	depends on !EFI_APP
 	hex "Text Base"
 	help

arch/mips/Kconfig

@@ -23,7 +23,11 @@ config TARGET_QEMU_MIPS
 
 config TARGET_MALTA
 	bool "Support malta"
+	select DM
+	select DM_SERIAL
 	select DYNAMIC_IO_PORT_BASE
+	select OF_CONTROL
+	select OF_ISA_BUS
 	select SUPPORTS_BIG_ENDIAN
 	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1

arch/mips/Makefile

@@ -4,6 +4,12 @@
 
 head-y := arch/mips/cpu/start.o
 
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+endif
+endif
+
 libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 

arch/mips/dts/Makefile

@@ -4,6 +4,7 @@
 
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 

arch/mips/dts/mti,malta.dts

+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00001000;	/* Exception vectors */
+/memreserve/ 0x000f0000 0x00010000;	/* PIIX4 ISA memory */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "mti,malta";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	isa@0 {
+		compatible = "isa";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <1 0 0 0x1000>;
+
+		uart0: serial@3f8 {
+			compatible = "ns16550a";
+
+			reg = <1 0x3f8 0x40>;
+			reg-shift = <0>;
+
+			clock-frequency = <1843200>;
+
+			u-boot,dm-pre-reloc;
+		};
+	};
+};

arch/mips/include/asm/global_data.h

@@ -15,14 +15,6 @@ struct arch_global_data {
 #ifdef CONFIG_DYNAMIC_IO_PORT_BASE
 	unsigned long io_port_base;
 #endif
-#ifdef CONFIG_JZSOC
-	/* There are other clocks in the jz4740 */
-	unsigned long per_clk;	/* Peripheral bus clock */
-	unsigned long dev_clk;	/* Device clock */
-	unsigned long sys_clk;
-	unsigned long tbl;
-	unsigned long lastinc;
-#endif
 #ifdef CONFIG_ARCH_ATH79
 	unsigned long id;
 	unsigned long soc;

arch/mips/mach-ath79/ar933x/ddr.c

@@ -268,6 +268,8 @@ void ddr_tap_tuning(void)
 	dir = 1;
 	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
 	val = tap;
+	upper = tap;
+	lower = tap;
 	while (!done) {
 		err = 0;
 

arch/mips/mach-ath79/include/mach/ar71xx_regs.h

@@ -660,6 +660,7 @@
 
 #define AR933X_RESET_GE1_MDIO				BIT(23)
 #define AR933X_RESET_GE0_MDIO				BIT(22)
+#define AR933X_RESET_ETH_SWITCH_ANALOG			BIT(14)
 #define AR933X_RESET_GE1_MAC				BIT(13)
 #define AR933X_RESET_WMAC				BIT(11)
 #define AR933X_RESET_GE0_MAC				BIT(9)

arch/mips/mach-ath79/reset.c

@@ -81,7 +81,8 @@ static int eth_init_ar933x(void)
 					  MAP_NOCACHE);
 	const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
 			 AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
-			 AR933X_RESET_ETH_SWITCH;
+			 AR933X_RESET_ETH_SWITCH |
+			 AR933X_RESET_ETH_SWITCH_ANALOG;
 
 	/* Clear MDIO slave EN bit. */
 	clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));

board/dbau1x00/Kconfig

@@ -9,6 +9,9 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "dbau1x00"
 
+config SYS_TEXT_BASE
+	default 0xbfc00000
+
 menu "dbau1x00 board options"
 
 choice

board/imgtec/malta/Kconfig

@@ -9,4 +9,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "malta"
 
+config SYS_TEXT_BASE
+	default 0xbe000000
+
 endif

board/imgtec/malta/malta.c

@@ -12,7 +12,6 @@
 #include <pci_gt64120.h>
 #include <pci_msc01.h>
 #include <rtc.h>
-#include <serial.h>
 
 #include <asm/addrspace.h>
 #include <asm/io.h>
@@ -161,18 +160,6 @@ int misc_init_r(void)
 	return 0;
 }
 
-struct serial_device *default_serial_console(void)
-{
-	switch (malta_sys_con()) {
-	case SYSCON_GT64120:
-		return &eserial1_device;
-
-	default:
-	case SYSCON_MSC01:
-		return &eserial2_device;
-	}
-}
-
 void pci_init_board(void)
 {
 	pci_dev_t bdf;

board/microchip/pic32mzda/Kconfig

@@ -10,4 +10,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "pic32mzdask"
 
+config SYS_TEXT_BASE
+	default 0x9d004000
+
 endif

board/micronas/vct/Kconfig

@@ -9,6 +9,9 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "vct"
 
+config SYS_TEXT_BASE
+	default 0x87000000
+
 menu "vct board options"
 
 choice

board/pb1x00/Kconfig

@@ -9,4 +9,7 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "pb1x00"
 
+config SYS_TEXT_BASE
+	default 0x83800000
+
 endif

board/qca/ap121/Kconfig

@@ -9,4 +9,7 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "ap121"
 
+config SYS_TEXT_BASE
+	default 0x9f000000
+
 endif

board/qca/ap143/Kconfig

@@ -9,4 +9,7 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "ap143"
 
+config SYS_TEXT_BASE
+	default 0x9f000000
+
 endif

board/qemu-mips/Kconfig

@@ -7,4 +7,8 @@ config SYS_CONFIG_NAME
 	default "qemu-mips" if 32BIT
 	default "qemu-mips64" if 64BIT
 
+config SYS_TEXT_BASE
+	default 0xbfc00000 if 32BIT
+	default 0xffffffffbfc00000 if 64BIT
+
 endif

board/tplink/wdr4300/Kconfig

@@ -12,4 +12,7 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "tplink_wdr4300"
 
+config SYS_TEXT_BASE
+	default 0xa1000000
+
 endif