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Commit 5afded6a authored by Roger Quadros's avatar Roger Quadros Committed by Tom Rini
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ARM: DRA7xx: Add PRCM and Control information for SATA


Adds the necessary PRCM and Control register information for
SATA on DRA7xx.

Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
parent afdc6321
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...@@ -376,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { ...@@ -376,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
struct omap_sys_ctrl_regs const dra7xx_ctrl = { struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_status = 0x4A002134, .control_status = 0x4A002134,
.control_phy_power_sata = 0x4A002374,
.control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518, .control_core_mac_id_0_hi = 0x4A002518,
.control_core_mac_id_1_lo = 0x4A00251C, .control_core_mac_id_1_lo = 0x4A00251C,
...@@ -895,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = { ...@@ -895,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l3init_hsusbhost_clkctrl = 0x4a009340, .cm_l3init_hsusbhost_clkctrl = 0x4a009340,
.cm_l3init_hsusbotg_clkctrl = 0x4a009348, .cm_l3init_hsusbotg_clkctrl = 0x4a009348,
.cm_l3init_hsusbtll_clkctrl = 0x4a009350, .cm_l3init_hsusbtll_clkctrl = 0x4a009350,
.cm_l3init_sata_clkctrl = 0x4a009388,
.cm_gmac_clkstctrl = 0x4a0093c0, .cm_gmac_clkstctrl = 0x4a0093c0,
.cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_gmac_gmac_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
/* cm2.l4per */ /* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700, .cm_l4per_clkstctrl = 0x4a009700,
......
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