ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039

When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.

Signed-off-by: Sricharan R <r.sricharan@ti.com>