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Commit 4c0620bf authored by Tom Rini's avatar Tom Rini Committed by Albert ARIBAUD
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am33xx: Add support, update omap3 McSPI driver


Signed-off-by: default avatarTom Rini <trini@ti.com>
parent 6bfca503
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...@@ -148,6 +148,11 @@ static void enable_per_clocks(void) ...@@ -148,6 +148,11 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl); writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL) while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
; ;
/* spi0 */
writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
;
} }
static void mpu_pll_config(void) static void mpu_pll_config(void)
......
...@@ -86,15 +86,21 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ...@@ -86,15 +86,21 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
case 0: case 0:
ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE; ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
break; break;
#ifdef OMAP3_MCSPI2_BASE
case 1: case 1:
ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE; ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
break; break;
#endif
#ifdef OMAP3_MCSPI3_BASE
case 2: case 2:
ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE; ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
break; break;
#endif
#ifdef OMAP3_MCSPI4_BASE
case 3: case 3:
ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE; ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
break; break;
#endif
default: default:
printf("SPI error: unsupported bus %i. \ printf("SPI error: unsupported bus %i. \
Supported busses 0 - 3\n", bus); Supported busses 0 - 3\n", bus);
......
...@@ -30,10 +30,15 @@ ...@@ -30,10 +30,15 @@
#ifndef _OMAP3_SPI_H_ #ifndef _OMAP3_SPI_H_
#define _OMAP3_SPI_H_ #define _OMAP3_SPI_H_
#ifdef CONFIG_AM33XX
#define OMAP3_MCSPI1_BASE 0x48030100
#define OMAP3_MCSPI2_BASE 0x481A0100
#else
#define OMAP3_MCSPI1_BASE 0x48098000 #define OMAP3_MCSPI1_BASE 0x48098000
#define OMAP3_MCSPI2_BASE 0x4809A000 #define OMAP3_MCSPI2_BASE 0x4809A000
#define OMAP3_MCSPI3_BASE 0x480B8000 #define OMAP3_MCSPI3_BASE 0x480B8000
#define OMAP3_MCSPI4_BASE 0x480BA000 #define OMAP3_MCSPI4_BASE 0x480BA000
#endif
#define OMAP3_MCSPI_MAX_FREQ 48000000 #define OMAP3_MCSPI_MAX_FREQ 48000000
......
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