Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

arch/arm/dts/zynq-zc706.dts

@@ -18,6 +18,7 @@
 		i2c0 = &i2c0;
 		serial0 = &uart1;
 		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {
@@ -291,6 +292,7 @@
 };
 
 &sdhci0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sdhci0_default>;

arch/arm/dts/zynq-zed.dts

@@ -17,6 +17,7 @@
 		ethernet0 = &gem0;
 		serial0 = &uart1;
 		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {
@@ -50,6 +51,7 @@
 };
 
 &sdhci0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 

arch/arm/dts/zynq-zybo.dts

@@ -16,6 +16,8 @@
 	aliases {
 		ethernet0 = &gem0;
 		serial0 = &uart1;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {
@@ -28,6 +30,10 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
 };
 
 &clkc {
@@ -45,6 +51,7 @@
 };
 
 &sdhci0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
@@ -52,3 +59,14 @@
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};

arch/arm/mach-zynq/Kconfig

@@ -33,7 +33,6 @@ config TARGET_ZYNQ_ZC770
 
 config TARGET_ZYNQ_ZYBO
 	bool "Zynq Zybo Board"
-	select ZYNQ_CUSTOM_INIT
 
 endchoice
 

arch/microblaze/Kconfig

@@ -11,6 +11,8 @@ choice
 config TARGET_MICROBLAZE_GENERIC
 	bool "Support microblaze-generic"
 	select SUPPORT_SPL
+	select OF_CONTROL
+	select DM
 
 endchoice
 

board/xilinx/microblaze-generic/microblaze-generic.c

@@ -69,6 +69,7 @@ int dram_init(void)
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_XILINX_GPIO
 	if (reset_pin != -1)
 		gpio_direction_output(reset_pin, 1);
@@ -77,7 +78,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_XILINX_TB_WATCHDOG
 	hw_watchdog_disable();
 #endif
-
+#endif
 	puts ("Reseting board\n");
 	__asm__ __volatile__ ("	mts rmsr, r0;" \
 				"bra r0");
@@ -122,40 +123,5 @@ int board_eth_init(bd_t *bis)
 			txpp, rxpp);
 #endif
 
-#ifdef CONFIG_XILINX_LL_TEMAC
-# ifdef XILINX_LLTEMAC_BASEADDR
-#  ifdef XILINX_LLTEMAC_FIFO_BASEADDR
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
-			XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
-#  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
-#   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
-			XILINX_LL_TEMAC_M_SDMA_DCR,
-			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
-#   else
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
-			XILINX_LL_TEMAC_M_SDMA_PLB,
-			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
-#   endif
-#  endif
-# endif
-# ifdef XILINX_LLTEMAC_BASEADDR1
-#  ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
-			XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
-#  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
-#   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
-			XILINX_LL_TEMAC_M_SDMA_DCR,
-			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
-#   else
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
-			XILINX_LL_TEMAC_M_SDMA_PLB,
-			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
-#   endif
-#  endif
-# endif
-#endif
-
 	return ret;
 }

board/xilinx/microblaze-generic/xparameters.h

@@ -56,12 +56,6 @@
 /* Ethernet controller is Ethernet_MAC */
 #define XILINX_EMACLITE_BASEADDR       0x40C00000
 
-/* LL_TEMAC Ethernet controller */
-#define XILINX_LLTEMAC_BASEADDR			0x44000000
-#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR	0x42000180
-#define XILINX_LLTEMAC_BASEADDR1		0x44200000
-#define XILINX_LLTEMAC_FIFO_BASEADDR1		0x42100000
-
 /* Watchdog IP is wxi_timebase_wdt_0 */
 #define XILINX_WATCHDOG_BASEADDR	0x50000000
 #define XILINX_WATCHDOG_IRQ		1

board/xilinx/zynq/Makefile

@@ -12,6 +12,7 @@ hw-platform-$(CONFIG_TARGET_ZYNQ_ZED)		:= zed_hw_platform
 hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED)	:= MicroZed_hw_platform
 hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702)		:= ZC702_hw_platform
 hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706)		:= ZC706_hw_platform
+hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO)		:= zybo_hw_platform
 # If you want to use customized ps7_init_gpl.c/h,
 # enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
 # This line must be placed at the bottom of the list because

board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h

+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*typedef unsigned int  u32; */
+
+/** do we need to make this name more unique ? **/
+/*extern u32 ps7_init_data[]; */
+extern unsigned long *ps7_ddr_init_data;
+extern unsigned long *ps7_mio_init_data;
+extern unsigned long *ps7_pll_init_data;
+extern unsigned long *ps7_clock_init_data;
+extern unsigned long *ps7_peripherals_init_data;
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ((OPCODE_EXIT      << 4) | 0)
+#define EMIT_CLEAR(addr)              ((OPCODE_CLEAR     << 4) | 1) , addr
+#define EMIT_WRITE(addr, val)          ((OPCODE_WRITE     << 4) | 2) , addr, val
+#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
+#define EMIT_MASKPOLL(addr, mask)      ((OPCODE_MASKPOLL  << 4) | 2) , addr, mask
+#define EMIT_MASKDELAY(addr, mask)      ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)	/* 0 is success in good old C */
+#define PS7_INIT_CORRUPT   (1)	/* 1 the data is corrupted, and slcr reg are in corrupted state now */
+#define PS7_INIT_TIMEOUT   (2)	/* 2 when a poll operation timed out */
+#define PS7_POLL_FAILED_DDR_INIT (3)	/* 3 when a poll operation timed out for ddr init */
+#define PS7_POLL_FAILED_DMA      (4)	/* 4 when a poll operation timed out for dma done bit */
+#define PS7_POLL_FAILED_PLL      (5)	/* 5 when a poll operation timed out for pll sequence init */
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  650000000
+#define DDR_FREQ  525000000
+#define DCI_FREQ  10096154
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  108333336
+#define WDT_FREQ  108333336
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  175000000
+#define FPGA2_FREQ  12264151
+#define FPGA3_FREQ  100000000
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config(unsigned long *);
+int ps7_init(void);
+int ps7_post_config(void);
+int ps7_debug(void);
+char *getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(void);
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif

configs/microblaze-generic_defconfig

 CONFIG_MICROBLAZE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_TARGET_MICROBLAZE_GENERIC=y
 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
 CONFIG_SPL=y
 CONFIG_SYS_PROMPT="U-Boot-mONStR> "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y

configs/zynq_microzed_defconfig

@@ -15,6 +15,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y

configs/zynq_picozed_defconfig

@@ -8,5 +8,4 @@ CONFIG_SPL=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y

configs/zynq_zc702_defconfig

@@ -14,7 +14,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_ZYNQ=y

configs/zynq_zc706_defconfig

@@ -15,6 +15,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y

configs/zynq_zc770_xm010_defconfig

@@ -17,7 +17,6 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQ_QSPI=y

configs/zynq_zc770_xm011_defconfig

@@ -12,5 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y

configs/zynq_zc770_xm012_defconfig

@@ -10,5 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y

configs/zynq_zc770_xm013_defconfig

@@ -12,5 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y

configs/zynq_zed_defconfig

@@ -15,6 +15,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y