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Commit 4398d559 authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by Joe Hershberger
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net: sh-eth: Add support Gigabit of SH7734


SH7734 support GMII. This add register infomation and the function
which enable GMII.

Signed-off-by: default avatarNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
parent ee6ec5d4
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...@@ -348,7 +348,7 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth) ...@@ -348,7 +348,7 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
phydev = phy_connect( phydev = phy_connect(
miiphy_get_dev_by_name(dev->name), miiphy_get_dev_by_name(dev->name),
port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII); port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
port_info->phydev = phydev; port_info->phydev = phydev;
phy_config(phydev); phy_config(phydev);
...@@ -405,6 +405,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) ...@@ -405,6 +405,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(TPAUSER_UNLIMITED, TPAUSER(port)); outl(TPAUSER_UNLIMITED, TPAUSER(port));
#endif #endif
#if defined(CONFIG_CPU_SH7734)
outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
#endif
/* Configure phy */ /* Configure phy */
ret = sh_eth_phy_config(eth); ret = sh_eth_phy_config(eth);
if (ret) { if (ret) {
...@@ -434,6 +437,12 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) ...@@ -434,6 +437,12 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(0, RTRATE(port)); outl(0, RTRATE(port));
#endif #endif
} }
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
else if (phy->speed == 1000) {
printf(SHETHER_NAME ": 1000Base/");
outl(GECMR_1000B, GECMR(port));
}
#endif
/* Check if full duplex mode is supported by the phy */ /* Check if full duplex mode is supported by the phy */
if (phy->duplex) { if (phy->duplex) {
......
...@@ -225,6 +225,7 @@ struct sh_eth_dev { ...@@ -225,6 +225,7 @@ struct sh_eth_dev {
#define GECMR(port) (BASE_IO_ADDR + 0x05b0) #define GECMR(port) (BASE_IO_ADDR + 0x05b0)
#define MAHR(port) (BASE_IO_ADDR + 0x05C0) #define MAHR(port) (BASE_IO_ADDR + 0x05C0)
#define MALR(port) (BASE_IO_ADDR + 0x05C8) #define MALR(port) (BASE_IO_ADDR + 0x05C8)
#define RMII_MII(port) (BASE_IO_ADDR + 0x0790)
#endif #endif
......
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