Skip to content
Snippets Groups Projects
Commit 35079aa9 authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak function


Instead of a #define use a null weak function for fsl_serdes_init

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent cb14e93b
No related branches found
No related tags found
No related merge requests found
...@@ -232,6 +232,12 @@ void cpu_init_f (void) ...@@ -232,6 +232,12 @@ void cpu_init_f (void)
invalidate_cpc(); invalidate_cpc();
} }
/* Implement a dummy function for those platforms w/o SERDES */
static void __fsl_serdes__init(void)
{
return ;
}
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
/* /*
* Initialize L2 as cache. * Initialize L2 as cache.
...@@ -375,10 +381,8 @@ int cpu_init_r(void) ...@@ -375,10 +381,8 @@ int cpu_init_r(void)
qe_reset(); qe_reset();
#endif #endif
#if defined(CONFIG_SYS_HAS_SERDES)
/* needs to be in ram since code uses global static vars */ /* needs to be in ram since code uses global static vars */
fsl_serdes_init(); fsl_serdes_init();
#endif
#if defined(CONFIG_MP) #if defined(CONFIG_MP)
setup_mp(); setup_mp();
......
...@@ -78,7 +78,6 @@ ...@@ -78,7 +78,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_SYS_HAS_SERDES /* has SERDES */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
......
...@@ -34,7 +34,6 @@ ...@@ -34,7 +34,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_HAS_SERDES /* has SERDES */
#define CONFIG_PHYS_64BIT #define CONFIG_PHYS_64BIT
#define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_ENABLE_36BIT_PHYS
......
...@@ -50,7 +50,6 @@ ...@@ -50,7 +50,6 @@
#define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE3 /* PCIE controler 3 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_HAS_SERDES /* has SERDES */
#define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SRIO2 /* SRIO port 2 */
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment