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Commit 33d88183 authored by Alexey Brodkin's avatar Alexey Brodkin Committed by Tom Rini
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Kconfig: move CONFIG_SYS_CLK_FREQ to Kconfig


It makes sense to specify CONFIG_SYS_CLK_FREQ in "configs/xx_defconfig"
instead of "include/configs/xxx.h" because then header will be reusable
across boards with different CPU clocks.

Also this nice to have an ability for end user to tune this value
himself via "menuconfig".

For now I'm only applying this change to all ARC configs because
otherwise scope of change will be huge.

Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Hans de Goede <hdegoede@redhat.com>
cc: Simon Glass <sjg@chromium.org>
Reviewed-by: default avatarTom Rini <trini@ti.com>
parent 9f9d8704
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...@@ -143,6 +143,12 @@ config SYS_TEXT_BASE ...@@ -143,6 +143,12 @@ config SYS_TEXT_BASE
help help
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
config SYS_CLK_FREQ
depends on ARC
int "CPU clock frequency"
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
endmenu # Boot images endmenu # Boot images
source "arch/Kconfig" source "arch/Kconfig"
......
CONFIG_ARC=y CONFIG_ARC=y
CONFIG_TARGET_ARCANGEL4_BE=y CONFIG_TARGET_ARCANGEL4_BE=y
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_ARC=y CONFIG_ARC=y
CONFIG_TARGET_ARCANGEL4=y CONFIG_TARGET_ARCANGEL4=y
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_ARC=y CONFIG_ARC=y
CONFIG_TARGET_AXS101=y CONFIG_TARGET_AXS101=y
CONFIG_SYS_CLK_FREQ=750000000
\ No newline at end of file
CONFIG_ARC=y CONFIG_ARC=y
CONFIG_TARGET_TB100=y CONFIG_TARGET_TB100=y
CONFIG_SYS_CLK_FREQ=500000000
\ No newline at end of file
...@@ -14,7 +14,6 @@ ...@@ -14,7 +14,6 @@
#define CONFIG_ARC700 #define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3 #define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_CLK_FREQ 70000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* /*
......
...@@ -13,7 +13,6 @@ ...@@ -13,7 +13,6 @@
#define CONFIG_ARC700 #define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3 #define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_CLK_FREQ 70000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* /*
......
...@@ -13,7 +13,6 @@ ...@@ -13,7 +13,6 @@
#define CONFIG_ARC700 #define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3 #define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_CLK_FREQ 750000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* NAND controller DMA doesn't work correctly with D$ enabled */ /* NAND controller DMA doesn't work correctly with D$ enabled */
......
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
#define CONFIG_ARC700 #define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3 #define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_CLK_FREQ 500000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* /*
......
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