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Commit 2c2b2183 authored by Ryan Harkin's avatar Ryan Harkin Committed by Tom Rini
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vexpress64: use 2nd DRAM bank only on juno


This patch makes the 2nd DRAM bank available on Juno only and not on
other vexpress64 targets, eg. the FVP models.

The commit below added a 2nd bank of NOR flash for Juno, but also for
all vexpress64 targets:

    commit 2d0cee1c
    Author: Liviu Dudau <Liviu.Dudau@foss.arm.com>
    Date:   Mon Oct 19 11:08:31 2015 +0100

    vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.

    Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
    Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: default avatarLiviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: default avatarRyan Harkin <ryan.harkin@linaro.org>
Tested-by: default avatarRyan Harkin <ryan.harkin@linaro.org>

Unfortunately, I only fully tested on Juno R0, R1 and the FVP Foundation
model.  Whilst FVP Base AEMV8 models run U-Boot OK, they fail to boot
the kernel.

Signed-off-by: default avatarRyan Harkin <ryan.harkin@linaro.org>
Acked-by: default avatarLiviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent bc8d3bc0
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...@@ -51,8 +51,10 @@ void dram_init_banksize(void) ...@@ -51,8 +51,10 @@ void dram_init_banksize(void)
{ {
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef PHYS_SDRAM_2
gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
} }
/* /*
......
...@@ -165,15 +165,20 @@ ...@@ -165,15 +165,20 @@
#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
/* Physical Memory Map */ /* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
#define PHYS_SDRAM_2 (0x880000000)
/* Top 16MB reserved for secure world use */ /* Top 16MB reserved for secure world use */
#define DRAM_SEC_SIZE 0x01000000 #define DRAM_SEC_SIZE 0x01000000
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
#define PHYS_SDRAM_2_SIZE 0x180000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_2 (0x880000000)
#define PHYS_SDRAM_2_SIZE 0x180000000
#else
#define CONFIG_NR_DRAM_BANKS 1
#endif
/* Enable memtest */ /* Enable memtest */
#define CONFIG_CMD_MEMTEST #define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
......
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