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Commit 2712f088 authored by Simon Glass's avatar Simon Glass
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x86: fdt: Create basic .dtsi file for coreboot


This contains just the minimum information for a coreboot-based board.

Signed-off-by: default avatarStefan Reinauer <reinauer@chromium.org>
Signed-off-by: default avatarGabe Black <gabeblack@chromium.org>
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
parent ba74a0ff
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/include/ "skeleton.dtsi"
/ {
aliases {
console = "/serial";
};
serial {
compatible = "ns16550";
reg-shift = <1>;
io-mapped = <1>;
multiplier = <1>;
baudrate = <115200>;
status = "disabled";
};
};
/*
* Skeleton device tree; the bare minimum needed to boot; just include and
* add a compatible value. The bootloader will typically populate the memory
* node.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
memory { device_type = "memory"; reg = <0 0>; };
};
/dts-v1/;
/include/ "coreboot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
......@@ -10,19 +12,11 @@
silent_console = <0>;
};
aliases {
console = "/serial@e0401000";
};
gpio: gpio {};
serial@e0401000 {
compatible = "ns16550";
reg = <0xe0401000 0x40>;
id = <1>;
reg-shift = <1>;
baudrate = <115200>;
clock-frequency = <4000000>;
multiplier = <1>;
status = "ok";
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
chosen { };
......
/dts-v1/;
/include/ "coreboot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
config {
silent_console = <0>;
};
gpio: gpio {};
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
};
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