Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

arch/arm/cpu/armv7/rmobile/Kconfig

@@ -6,6 +6,9 @@ choice
 config TARGET_ARMADILLO_800EVA
 	bool "armadillo 800 eva board"
 
+config TARGET_GOSE
+	bool "Gose board"
+
 config TARGET_KOELSCH
 	bool "Koelsch board"
 
@@ -29,6 +32,7 @@ config RMOBILE_EXTRAM_BOOT
 	default n
 
 source "board/atmark-techno/armadillo-800eva/Kconfig"
+source "board/renesas/gose/Kconfig"
 source "board/renesas/koelsch/Kconfig"
 source "board/renesas/lager/Kconfig"
 source "board/kmc/kzm9g/Kconfig"

arch/arm/cpu/armv7/rmobile/Makefile

@@ -13,6 +13,7 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
 obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o

arch/arm/cpu/armv7/rmobile/cpu_info.c

@@ -53,6 +53,7 @@ static const struct {
 	{ 0x40, "R8A7740" },
 	{ 0x45, "R8A7790" },
 	{ 0x47, "R8A7791" },
+	{ 0x4B, "R8A7793" },
 	{ 0x4C, "R8A7794" },
 	{ 0x0, "CPU" },
 };

arch/arm/include/asm/arch-rmobile/gpio.h

@@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void);
 #elif defined(CONFIG_R8A7791)
 #include "r8a7791-gpio.h"
 void r8a7791_pinmux_init(void);
+#elif defined(CONFIG_R8A7793)
+#include "r8a7793-gpio.h"
+void r8a7793_pinmux_init(void);
 #elif defined(CONFIG_R8A7794)
 #include "r8a7794-gpio.h"
 void r8a7794_pinmux_init(void);

arch/arm/include/asm/arch-rmobile/r8a7790.h

@@ -11,6 +11,10 @@
 
 #include "rcar-base.h"
 
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
+#define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
+
 #define R8A7790_CUT_ES2X	2
 #define IS_R8A7790_ES2()	\
 	(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)

arch/arm/include/asm/arch-rmobile/r8a7791.h

@@ -13,6 +13,10 @@
 /*
  * R-Car (R8A7791) I/O Addresses
  */
+
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
+
 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
 #define DBSC3_1_QOS_R1_BASE	0xE67A1100
 #define DBSC3_1_QOS_R2_BASE	0xE67A1200

arch/arm/include/asm/arch-rmobile/r8a7793.h

+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7793.h
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_R8A7793_H
+#define __ASM_ARCH_R8A7793_H
+
+#include "rcar-base.h"
+
+/*
+ * R8A7793 I/O Addresses
+ */
+
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
+
+#define DBSC3_1_QOS_R0_BASE	0xE67A1000
+#define DBSC3_1_QOS_R1_BASE	0xE67A1100
+#define DBSC3_1_QOS_R2_BASE	0xE67A1200
+#define DBSC3_1_QOS_R3_BASE	0xE67A1300
+#define DBSC3_1_QOS_R4_BASE	0xE67A1400
+#define DBSC3_1_QOS_R5_BASE	0xE67A1500
+#define DBSC3_1_QOS_R6_BASE	0xE67A1600
+#define DBSC3_1_QOS_R7_BASE	0xE67A1700
+#define DBSC3_1_QOS_R8_BASE	0xE67A1800
+#define DBSC3_1_QOS_R9_BASE	0xE67A1900
+#define DBSC3_1_QOS_R10_BASE	0xE67A1A00
+#define DBSC3_1_QOS_R11_BASE	0xE67A1B00
+#define DBSC3_1_QOS_R12_BASE	0xE67A1C00
+#define DBSC3_1_QOS_R13_BASE	0xE67A1D00
+#define DBSC3_1_QOS_R14_BASE	0xE67A1E00
+#define DBSC3_1_QOS_R15_BASE	0xE67A1F00
+#define DBSC3_1_QOS_W0_BASE	0xE67A2000
+#define DBSC3_1_QOS_W1_BASE	0xE67A2100
+#define DBSC3_1_QOS_W2_BASE	0xE67A2200
+#define DBSC3_1_QOS_W3_BASE	0xE67A2300
+#define DBSC3_1_QOS_W4_BASE	0xE67A2400
+#define DBSC3_1_QOS_W5_BASE	0xE67A2500
+#define DBSC3_1_QOS_W6_BASE	0xE67A2600
+#define DBSC3_1_QOS_W7_BASE	0xE67A2700
+#define DBSC3_1_QOS_W8_BASE	0xE67A2800
+#define DBSC3_1_QOS_W9_BASE	0xE67A2900
+#define DBSC3_1_QOS_W10_BASE	0xE67A2A00
+#define DBSC3_1_QOS_W11_BASE	0xE67A2B00
+#define DBSC3_1_QOS_W12_BASE	0xE67A2C00
+#define DBSC3_1_QOS_W13_BASE	0xE67A2D00
+#define DBSC3_1_QOS_W14_BASE	0xE67A2E00
+#define DBSC3_1_QOS_W15_BASE	0xE67A2F00
+
+#define DBSC3_1_DBADJ2		0xE67A00C8
+
+/*
+ * R8A7793 I/O Product Information
+ */
+#define R8A7793_CUT_ES2X	2
+#define IS_R8A7793_ES2() \
+	(rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
+
+#endif /* __ASM_ARCH_R8A7793_H */

arch/arm/include/asm/arch-rmobile/r8a7794.h

@@ -11,4 +11,7 @@
 
 #include "rcar-base.h"
 
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
+
 #endif /* __ASM_ARCH_R8A7794_H */

arch/arm/include/asm/arch-rmobile/rcar-base.h

@@ -10,7 +10,7 @@
 #define __ASM_ARCH_RCAR_BASE_H
 
 /*
- * R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses
  */
 #define RWDT_BASE		0xE6020000
 #define SWDT_BASE		0xE6030000
@@ -29,6 +29,20 @@
 #define SCIF4_BASE		0xE6EE0000
 #define SCIF5_BASE		0xE6EE8000
 
+/*
+ * SH-I2C
+ * Ch2 and ch3 are different address. These are defined
+ * in the header of each SoCs.
+ */
+#define CONFIG_SYS_I2C_SH_BASE0	0xE6500000
+#define CONFIG_SYS_I2C_SH_BASE1	0xE6510000
+
+/* RCAR-I2C */
+#define CONFIG_SYS_RCAR_I2C0_BASE	0xE6508000
+#define CONFIG_SYS_RCAR_I2C1_BASE	0xE6518000
+#define CONFIG_SYS_RCAR_I2C2_BASE	0xE6530000
+#define CONFIG_SYS_RCAR_I2C3_BASE	0xE6540000
+
 #define S3C_BASE		0xE6784000
 #define S3C_INT_BASE		0xE6784A00
 #define S3C_MEDIA_BASE		0xE6784B00

arch/arm/include/asm/arch-rmobile/rmobile.h

@@ -10,6 +10,8 @@
 #include <asm/arch/r8a7790.h>
 #elif defined(CONFIG_R8A7791)
 #include <asm/arch/r8a7791.h>
+#elif defined(CONFIG_R8A7793)
+#include <asm/arch/r8a7793.h>
 #elif defined(CONFIG_R8A7794)
 #include <asm/arch/r8a7794.h>
 #else

board/renesas/alt/alt.c

@@ -49,6 +49,10 @@ void s_init(void)
 #define SMSTPCR8	0xE6150990
 #define ETHER_MSTP813	(1 << 13)
 
+#define MSTPSR3		0xE6150048
+#define SMSTPCR3	0xE615013C
+#define IIC1_MSTP323	(1 << 23)
+
 #define mstp_setbits(type, addr, saddr, set) \
 	out_##type((saddr), in_##type(addr) | (set))
 #define mstp_clrbits(type, addr, saddr, clear) \
@@ -69,6 +73,9 @@ int board_early_init_f(void)
 	/* ETHER */
 	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
 
+	/* IIC1 / sh-i2c ch1 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
+
 	return 0;
 }
 
@@ -81,7 +88,7 @@ void arch_preboot_os(void)
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	/* Init PFC controller */
 	r8a7794_pinmux_init();
@@ -149,23 +156,11 @@ const struct rmobile_sysinfo sysinfo = {
 	CONFIG_RMOBILE_BOARD_STRING
 };
 
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
-}
-
-int board_late_init(void)
-{
-	return 0;
-}
-
 void reset_cpu(ulong addr)
 {
 	u8 val;
 
-	i2c_set_bus_num(1); /* PowerIC connected to ch3 */
-	i2c_init(400000, 0);
+	i2c_set_bus_num(1); /* PowerIC connected to ch1 */
 	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 	val |= 0x02;
 	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);

board/renesas/gose/Kconfig

+if TARGET_GOSE
+
+config SYS_BOARD
+	default "gose"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "gose"
+
+endif

board/renesas/gose/MAINTAINERS

+ALT BOARD
+M:	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S:	Maintained
+F:	board/renesas/gose/
+F:	include/configs/gose.h
+F:	configs/gose_defconfig

board/renesas/gose/Makefile

+#
+# board/renesas/alt/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= gose.o qos.o

board/renesas/gose/gose.c

+/*
+ * board/renesas/gose/gose.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 stc;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 1.5GHz */
+	stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+	/* QoS */
+	qos_init();
+}
+
+#define MSTPSR1		0xE6150038
+#define SMSTPCR1	0xE6150134
+#define TMU0_MSTP125	(1 << 25)
+
+#define MSTPSR7		0xE61501C4
+#define SMSTPCR7	0xE615014C
+#define SCIF0_MSTP721	(1 << 21)
+
+#define MSTPSR8		0xE61509A0
+#define SMSTPCR8	0xE6150990
+#define ETHER_MSTP813	(1 << 13)
+
+#define mstp_setbits(type, addr, saddr, set) \
+	out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+	out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+	mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+	mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/* SCIF0 */
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/* ETHER */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+	return 0;
+}
+
+#define TSTR0		0x04
+#define TSTR0_STR0	0x01
+void arch_preboot_os(void)
+{
+	/* stop TMU0 */
+	mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
+	/* Disable TMU0 */
+	mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
+#define PUPR5		0xE6060114
+#define PUPR5_ETH	0x3FFC0000
+#define PUPR5_ETH_MAGIC	(1 << 27)
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7793_pinmux_init();
+
+	/* ETHER Enable */
+	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+	gpio_request(GPIO_FN_ETH_RXD0, NULL);
+	gpio_request(GPIO_FN_ETH_RXD1, NULL);
+	gpio_request(GPIO_FN_ETH_LINK, NULL);
+	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+	gpio_request(GPIO_FN_ETH_MDIO, NULL);
+	gpio_request(GPIO_FN_ETH_TXD1, NULL);
+	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+	gpio_request(GPIO_FN_ETH_TXD0, NULL);
+	gpio_request(GPIO_FN_ETH_MDC, NULL);
+	gpio_request(GPIO_FN_IRQ0, NULL);
+
+	mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
+	gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
+	mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
+
+	gpio_direction_output(GPIO_GP_5_22, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_5_22, 1);
+	udelay(1);
+
+	return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+
+int board_eth_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+	u32 val;
+	unsigned char enetaddr[6];
+
+#ifdef CONFIG_SH_ETHER
+	ret = sh_eth_initialize(bis);
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		return ret;
+
+	/* Set Mac address */
+	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+	    enetaddr[2] << 8 | enetaddr[3];
+	writel(val, CXR24);
+
+	val = enetaddr[4] << 8 | enetaddr[5];
+	writel(val, CXR25);
+#endif
+
+	return ret;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+	u8 val;
+
+	i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+	val |= 0x02;
+	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}

board/renesas/gose/qos.h

+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif

board/renesas/koelsch/koelsch.c

@@ -90,7 +90,7 @@ void arch_preboot_os(void)
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	/* Init PFC controller */
 	r8a7791_pinmux_init();
@@ -173,17 +173,6 @@ const struct rmobile_sysinfo sysinfo = {
 	CONFIG_RMOBILE_BOARD_STRING
 };
 
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
-}
-
-int board_late_init(void)
-{
-	return 0;
-}
-
 void reset_cpu(ulong addr)
 {
 	u8 val;