Skip to content
Snippets Groups Projects
Commit 221838cc authored by Jason Jin's avatar Jason Jin Committed by Wolfgang Denk
Browse files

Remove the bios emulator from MAI board.


The bios emulator in the MAI board can not pass compile
and have a lot of crap in it. remove it and will have a
clean and small bios emulator in the drivers directory
which can be uesed for every board.

Signed-off-by: default avatarJason Jin <Jason.jin@freescale.com>
parent 56183324
No related branches found
No related tags found
No related merge requests found
Showing
with 0 additions and 1510 deletions
/*
* Mostly done after the Scitech Bios emulation
* Written by Hans-Jrg Frieden
* Hyperion Entertainment
*/
#include "x86emu.h"
#include "glue.h"
#undef DEBUG
#ifdef DEBUG
#define PRINTF(fmt, args...) printf(fmt, ## args)
#else
#define PRINTF(fmt, args...)
#endif
#define BIOS_SEG 0xFFF0
#define PCIBIOS_SUCCESSFUL 0
#define PCIBIOS_DEVICE_NOT_FOUND 0x86
typedef unsigned char UBYTE;
typedef unsigned short UWORD;
typedef unsigned long ULONG;
typedef char BYTE;
typedef short WORT;
typedef long LONG;
static inline UBYTE read_byte(volatile UBYTE* from)
{
int x;
asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from));
return (UBYTE)x;
}
static inline void write_byte(volatile UBYTE *to, int x)
{
asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x));
}
static inline UWORD read_word_little(volatile UWORD *from)
{
int x;
asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from));
return (UWORD)x;
}
static inline UWORD read_word_big(volatile UWORD *from)
{
int x;
asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from));
return (UWORD)x;
}
static inline void write_word_little(volatile UWORD *to, int x)
{
asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to));
}
static inline void write_word_big(volatile UWORD *to, int x)
{
asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x));
}
static inline ULONG read_long_little(volatile ULONG *from)
{
unsigned long x;
asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from));
return (ULONG)x;
}
static inline ULONG read_long_big(volatile ULONG *from)
{
unsigned long x;
asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from));
return (ULONG)x;
}
static inline void write_long_little(volatile ULONG *to, ULONG x)
{
asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to));
}
static inline void write_long_big(volatile ULONG *to, ULONG x)
{
asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x));
}
#define port_to_mem(from) (0xFE000000|(from))
#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from))
#define in_word(from) read_word_little((UWORD *)port_to_mem(from))
#define in_long(from) read_long_little((ULONG *)port_to_mem(from))
#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val)
#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val)
#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val)
static void X86API undefined_intr(int intno)
{
extern u16 A1_rdw(u32 addr);
if (A1_rdw(intno * 4 + 2) == BIOS_SEG)
{
PRINTF("Undefined interrupt %xh called AX = %xh, BX = %xh, CX = %xh, DX = %xh\n",
intno, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
X86EMU_halt_sys();
}
else
{
PRINTF("Calling interrupt %xh, AL=%xh, AH=%xh\n", intno, M.x86.R_AL, M.x86.R_AH);
X86EMU_prepareForInt(intno);
}
}
static void X86API int42(int intno);
static void X86API int15(int intno);
static void X86API int10(int intno)
{
if (A1_rdw(intno*4+2) == BIOS_SEG)
int42(intno);
else
{
PRINTF("int10: branching to %04X:%04X, AL=%xh, AH=%xh\n", A1_rdw(intno*4+2), A1_rdw(intno*4),
M.x86.R_AL, M.x86.R_AH);
X86EMU_prepareForInt(intno);
}
}
static void X86API int1A(int intno)
{
int device;
switch(M.x86.R_AX)
{
case 0xB101: /* PCI Bios Present? */
M.x86.R_AL = 0x00;
M.x86.R_EDX = 0x20494350;
M.x86.R_BX = 0x0210;
M.x86.R_CL = 3;
CLEAR_FLAG(F_CF);
break;
case 0xB102: /* Find device */
device = mypci_find_device(M.x86.R_DX, M.x86.R_CX, M.x86.R_SI);
if (device != -1)
{
M.x86.R_AH = PCIBIOS_SUCCESSFUL;
M.x86.R_BH = mypci_bus(device);
M.x86.R_BL = mypci_devfn(device);
}
else
{
M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND;
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
break;
case 0xB103: /* Find PCI class code */
M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND;
/*printf("Find by class not yet implmented"); */
CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
break;
case 0xB108: /* read config byte */
M.x86.R_CL = mypci_read_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
M.x86.R_AH = PCIBIOS_SUCCESSFUL;
CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
/*printf("read_config_byte %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
/* M.x86.R_CL); */
break;
case 0xB109: /* read config word */
M.x86.R_CX = mypci_read_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
M.x86.R_AH = PCIBIOS_SUCCESSFUL;
CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
/*printf("read_config_word %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
/* M.x86.R_CX); */
break;
case 0xB10A: /* read config dword */
M.x86.R_ECX = mypci_read_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
M.x86.R_AH = PCIBIOS_SUCCESSFUL;
CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
/*printf("read_config_long %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
/* M.x86.R_ECX); */
break;
case 0xB10B: /* write config byte */
mypci_write_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CL);
M.x86.R_AH = PCIBIOS_SUCCESSFUL;
CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
/*printf("write_config_byte %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
/* M.x86.R_CL); */
break;
case 0xB10C: /* write config word */
mypci_write_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CX);
M.x86.R_AH = PCIBIOS_SUCCESSFUL;
CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
/*printf("write_config_word %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
/* M.x86.R_CX); */
break;
case 0xB10D: /* write config dword */
mypci_write_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_ECX);
M.x86.R_AH = PCIBIOS_SUCCESSFUL;
CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
/*printf("write_config_long %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
/* M.x86.R_ECX); */
break;
default:
PRINTF("BIOS int %xh: Unknown function AX=%04xh\n", intno, M.x86.R_AX);
}
}
void bios_init(void)
{
int i;
X86EMU_intrFuncs bios_intr_tab[256];
for (i=0; i<256; i++)
{
write_long_little(M.mem_base+i*4, BIOS_SEG<<16);
bios_intr_tab[i] = undefined_intr;
}
bios_intr_tab[0x10] = int10;
bios_intr_tab[0x1A] = int1A;
bios_intr_tab[0x42] = int42;
bios_intr_tab[0x15] = int15;
bios_intr_tab[0x6D] = int42;
X86EMU_setupIntrFuncs(bios_intr_tab);
video_init();
}
unsigned char setup_40x25[] =
{
0x38, 0x28, 0x2d, 0x0a, 0x1f, 6, 0x19,
0x1c, 2, 7, 6, 7, 0, 0, 0, 0
};
unsigned char setup_80x25[] =
{
0x71, 0x50, 0x5a, 0x0a, 0x1f, 6, 0x19,
0x1c, 2, 7, 6, 7, 0, 0, 0, 0
};
unsigned char setup_graphics[] =
{
0x38, 0x28, 0x20, 0x0a, 0x7f, 6, 0x64,
0x70, 2, 1, 6, 7, 0, 0, 0, 0
};
unsigned char setup_bw[] =
{
0x61, 0x50, 0x52, 0x0f, 0x19, 6, 0x19,
0x19, 2, 0x0d, 0x0b, 0x0c, 0, 0, 0, 0
};
unsigned char * setup_modes[] =
{
setup_40x25, /* mode 0: 40x25 bw text */
setup_40x25, /* mode 1: 40x25 col text */
setup_80x25, /* mode 2: 80x25 bw text */
setup_80x25, /* mode 3: 80x25 col text */
setup_graphics, /* mode 4: 320x200 col graphics */
setup_graphics, /* mode 5: 320x200 bw graphics */
setup_graphics, /* mode 6: 640x200 bw graphics */
setup_bw /* mode 7: 80x25 mono text */
};
unsigned int setup_cols[] =
{
40, 40, 80, 80, 40, 40, 80, 80
};
unsigned char setup_modesets[] =
{
0x2C, 0x28, 0x2D, 0x29, 0x2A, 0x2E, 0x1E, 0x29
};
unsigned int setup_bufsize[] =
{
2048, 2048, 4096, 2096, 16384, 16384, 16384, 4096
};
void bios_set_mode(int mode)
{
int i;
unsigned char mode_set = setup_modesets[mode]; /* Control register value */
unsigned char *setup_regs = setup_modes[mode]; /* Register 3D4 Array */
/* Switch video off */
out_byte(0x3D8, mode_set & 0x37);
/* Set up parameters at 3D4h */
for (i=0; i<16; i++)
{
out_byte(0x3D4, (unsigned char)i);
out_byte(0x3D5, *setup_regs);
setup_regs++;
}
/* Enable video */
out_byte(0x3D8, mode_set);
/* Set overscan */
if (mode == 6) out_byte(0x3D9, 0x3F);
else out_byte(0x3D9, 0x30);
}
static void bios_print_string(void)
{
extern void video_bios_print_string(char *string, int x, int y, int attr, int count);
char *s = (char *)(M.x86.R_ES<<4) + M.x86.R_BP;
int attr;
if (M.x86.R_AL & 0x02) attr = - 1;
else attr = M.x86.R_BL;
video_bios_print_string(s, M.x86.R_DH, M.x86.R_DL, attr, M.x86.R_CX);
}
static void X86API int42(int intno)
{
switch (M.x86.R_AH)
{
case 0x00:
bios_set_mode(M.x86.R_AL);
break;
case 0x13:
bios_print_string();
break;
default:
PRINTF("Warning: VIDEO BIOS interrupt %xh unimplemented function %xh, AL = %xh\n",
intno, M.x86.R_AH, M.x86.R_AL);
}
}
static void X86API int15(int intno)
{
PRINTF("Called interrupt 15h: AX = %xh, BX = %xh, CX = %xh, DX = %xh\n",
M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
}
#include <common.h>
#include <pci.h>
#include <74xx_7xx.h>
#ifdef DEBUG
#undef DEBUG
#endif
#ifdef DEBUG
#define PRINTF(format, args...) _printf(format , ## args)
#else
#define PRINTF(format, argc...)
#endif
static pci_dev_t to_pci(int bus, int devfn)
{
return PCI_BDF(bus, (devfn>>3), devfn&3);
}
int mypci_find_device(int vendor, int product, int index)
{
return pci_find_device(vendor, product, index);
}
int mypci_bus(int device)
{
return PCI_BUS(device);
}
int mypci_devfn(int device)
{
return (PCI_DEV(device)<<3) | PCI_FUNC(device);
}
#define mypci_read_func(type, size) \
type mypci_read_cfg_##size##(int bus, int devfn, int offset) \
{ \
type c; \
pci_read_config_##size##(to_pci(bus, devfn), offset, &c); \
return c; \
}
#define mypci_write_func(type, size) \
void mypci_write_cfg_##size##(int bus, int devfn, int offset, int value) \
{ \
pci_write_config_##size##(to_pci(bus, devfn), offset, value); \
}
mypci_read_func(u8,byte);
mypci_read_func(u16,word);
mypci_write_func(u8,byte);
mypci_write_func(u16,word);
u32 mypci_read_cfg_long(int bus, int devfn, int offset)
{
u32 c;
pci_read_config_dword(to_pci(bus, devfn), offset, &c);
return c;
}
void mypci_write_cfg_long(int bus, int devfn, int offset, int value)
{
pci_write_config_dword(to_pci(bus, devfn), offset, value);
}
void _printf(const char *fmt, ...)
{
va_list args;
char buf[CFG_PBSIZE];
va_start(args, fmt);
(void)vsprintf(buf, fmt, args);
va_end(args);
printf(buf);
}
char *_getenv(char *name)
{
return getenv(name);
}
unsigned long get_bar_size(pci_dev_t dev, int offset)
{
u32 bar_back, bar_value;
/* Save old BAR value */
pci_read_config_dword(dev, offset, &bar_back);
/* Write all 1's. */
pci_write_config_dword(dev, offset, ~0);
/* Now read back the relevant bits */
pci_read_config_dword(dev, offset, &bar_value);
/* Restore original value */
pci_write_config_dword(dev, offset, bar_back);
if (bar_value == 0) return 0xFFFFFFFF; /* This BAR is disabled */
if ((bar_value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY)
{
/* This is a memory space BAR. Mask it out so we get the size of it */
return ~(bar_value & PCI_BASE_ADDRESS_MEM_MASK) + 1;
}
/* Not suitable */
return 0xFFFFFFFF;
}
void enable_compatibility_hole(void)
{
u8 cfg;
pci_dev_t art = PCI_BDF(0,0,0);
pci_read_config_byte(art, 0x54, &cfg);
/* cfg |= 0x08; */
cfg |= 0x20;
pci_write_config_byte(art, 0x54, cfg);
}
void disable_compatibility_hole(void)
{
u8 cfg;
pci_dev_t art = PCI_BDF(0,0,0);
pci_read_config_byte(art, 0x54, &cfg);
/* cfg &= ~0x08; */
cfg &= ~0x20;
pci_write_config_byte(art, 0x54, cfg);
}
void map_rom(pci_dev_t dev, u32 address)
{
pci_write_config_dword(dev, PCI_ROM_ADDRESS, address|PCI_ROM_ADDRESS_ENABLE);
}
void unmap_rom(pci_dev_t dev)
{
pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
}
void bat_map(u8 batnum, u32 address, u32 length)
{
u32 temp = address;
address &= 0xFFFE0000;
temp &= 0x0001FFFF;
length = (length - 1 ) >> 17;
length <<= 2;
switch (batnum)
{
case 0:
__asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3));
__asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22));
break;
case 1:
__asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3));
__asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22));
break;
case 2:
__asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3));
__asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22));
break;
case 3:
__asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3));
__asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22));
break;
}
}
int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size);
int attempt_map_rom(pci_dev_t dev, void *copy_address)
{
u32 rom_size = 0;
u32 rom_address = 0;
u32 bar_size = 0;
u32 bar_backup = 0;
int i,j;
void *image = 0;
u32 image_size = 0;
int did_correct = 0;
u32 prefetch_addr = 0;
u32 prefetch_size = 0;
u32 prefetch_idx = 0;
/* Get the size of the expansion rom */
pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0xFFFFFFFF);
pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_size);
if ((rom_size & 0x01) == 0)
{
PRINTF("No ROM\n");
return 0;
}
rom_size &= 0xFFFFF800;
rom_size = (~rom_size)+1;
PRINTF("ROM Size is %dK\n", rom_size/1024);
/*
* Try to find a place for the ROM. We always attempt to use
* one of the card's bases for this, as this will be in any
* bridge's resource range as well as being free of conflicts
* with other cards. In a graphics card it is very unlikely
* that there won't be any base address that is large enough to
* hold the rom.
*
* FIXME: To work around this, theoretically the largest base
* could be used if none is found in the loop below.
*/
for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4)
{
bar_size = get_bar_size(dev, i);
PRINTF("PCI_BASE_ADDRESS_%d is %dK large\n",
(i - PCI_BASE_ADDRESS_0)/4,
bar_size/1024);
if (bar_size != 0xFFFFFFFF && bar_size >= rom_size)
{
PRINTF("Found a match for rom size\n");
pci_read_config_dword(dev, i, &rom_address);
rom_address &= 0xFFFFFFF0;
if (rom_address != 0 && rom_address != 0xFFFFFFF0) break;
}
}
if (rom_address == 0 || rom_address == 0xFFFFFFF0)
{
PRINTF("No suitable rom address found\n");
return 0;
}
/* Disable the BAR */
pci_read_config_dword(dev, i, &bar_backup);
pci_write_config_dword(dev, i, 0);
/* Map ROM */
pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address | PCI_ROM_ADDRESS_ENABLE);
/* Copy the rom to a place in the emulator space */
PRINTF("Claiming BAT 2\n");
bat_map(2, rom_address, rom_size);
/* show_bat_mapping(); */
if (0 == find_image(rom_address, rom_size, &image, &image_size))
{
PRINTF("No x86 BIOS image found\n");
return 0;
}
PRINTF("Copying %ld bytes from 0x%lx to 0x%lx\n", (long)image_size, (long)image, (long)copy_address);
/* memcpy(copy_address, rom_address, rom_size); */
{
unsigned char *from = (unsigned char *)image; /* rom_address; */
unsigned char *to = (unsigned char *)copy_address;
for (j=0; j<image_size /*rom_size*/; j++)
{
*to++ = *from++;
}
}
PRINTF("Copy is done\n");
/* Unmap the ROM and restore the BAR */
pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
pci_write_config_dword(dev, i, bar_backup);
/* FIXME: Shouldn't be needed anymore*/
/* bat_map(2, 0x80000000, 256*1024*1024);
show_bat_mapping(); */
/*
* Since most cards can probably only do 16 bit IO addressing, we
* correct their IO base into an appropriate value.
* This should do for most.
*/
for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4)
{
unsigned long value;
pci_read_config_dword(dev, i, &value);
if (value & 0x01) /* IO */
{
did_correct = 1;
pci_write_config_dword(dev, i, 0x1001);
break;
}
if (value & PCI_BASE_ADDRESS_MEM_PREFETCH)
{
prefetch_idx = i;
prefetch_addr = value & PCI_BASE_ADDRESS_MEM_MASK;
prefetch_size = get_bar_size(dev, i);
}
}
if (1) /* did_correct) */
{
extern pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr);
int busnr = PCI_BUS(dev);
if (busnr)
{
pci_dev_t bridge;
PRINTF("Need to correct bridge device for IO range change\n");
bridge = pci_find_bridge_for_bus(NULL, busnr);
if (bridge == PCI_ANY_ID)
{
PRINTF("Didn't find bridge. Hope that's OK\n");
}
else
{
/*
* Set upper I/O base/limit to 0
*/
pci_write_config_byte(bridge, 0x30, 0x00);
pci_write_config_byte(bridge, 0x31, 0x00);
pci_write_config_byte(bridge, 0x32, 0x00);
pci_write_config_byte(bridge, 0x33, 0x00);
if (did_correct)
{
/*
* set lower I/O base to 1000
* That is, bits 0:3 are set to 0001 by default.
* bits 7:4 contain I/O address bits 15:12
* all others are assumed 0.
*/
pci_write_config_byte(bridge, 0x1C, 0x11);
/*
* Set lower I/O limit to 1FFF
* That is, bits 0:3 are reserved and always 0000
* Bits 7:4 contain I/O address bits 15:12
* All others are assumed F.
*/
pci_write_config_byte(bridge, 0x1D, 0x10);
pci_write_config_byte(bridge, 0x0D, 0x20);
PRINTF("Corrected bridge resource range of bridge at %02x:%02x:%02x\n",
PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
}
else
{
/*
* This card doesn't have I/O, we disable I/O forwarding
*/
pci_write_config_byte(bridge, 0x1C, 0x11);
pci_write_config_byte(bridge, 0x1D, 0x00);
pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0);
pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0);
pci_write_config_dword(bridge, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_IO);
PRINTF("Disabled bridge resource range of bridge at %02x:%02x:%02x\n",
PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
}
}
/*
* Correct the prefetchable memory base, which is not set correctly by
* the U-Boot autoconfig stuff
*/
if (prefetch_idx)
{
/* PRINTF("Setting prefetchable range to %x, %x (%x and %x)\n", */
/* prefetch_addr, prefetch_addr+prefetch_size, */
/* prefetch_addr>>16, (prefetch_addr+prefetch_size)>>16); */
/* pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, (prefetch_addr>>16)); */
/* pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, (prefetch_addr+prefetch_size)>>16); */
}
pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, 0x1000);
pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, 0x0000);
pci_write_config_byte(bridge, 0xD0, 0x0A);
pci_write_config_byte(bridge, 0xD3, 0x04);
/*
* Set the interrupt pin to 0
*/
#if 0
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0);
pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 0);
#endif
pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0);
pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0);
}
}
/* Finally, enable the card's IO and memory response */
pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0);
return 1;
}
int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size)
{
int i = 0;
unsigned char *rom = (unsigned char *)rom_address;
/* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; /* No bios rom this is, yes. */ */
for (;;)
{
unsigned short pci_data_offset = *(rom+0x18) + 256 * *(rom+0x19);
unsigned short pci_image_length = (*(rom+pci_data_offset+0x10) + 256 * *(rom+pci_data_offset+0x11)) * 512;
unsigned char pci_image_type = *(rom+pci_data_offset+0x14);
if (*rom != 0x55 || *(rom+1) != 0xAA)
{
PRINTF("Invalid header this is\n");
return 0;
}
PRINTF("Image %i: Type %d (%s)\n", i++, pci_image_type,
pci_image_type==0 ? "x86" :
pci_image_type==1 ? "OpenFirmware" :
"Unknown");
if (pci_image_type == 0)
{
*image = rom;
*image_size = pci_image_length;
return 1;
}
if (*(rom+pci_data_offset+0x15) & 0x80)
{
PRINTF("LAST image encountered, no image found\n");
return 0;
}
rom += pci_image_length;
}
}
void show_bat_mapping(void)
{
u32 dbat0u, dbat0l, ibat0u, ibat0l;
u32 dbat1u, dbat1l, ibat1u, ibat1l;
u32 dbat2u, dbat2l, ibat2u, ibat2l;
u32 dbat3u, dbat3l, ibat3u, ibat3l;
u32 msr, hid0, l2cr_reg;
__asm volatile ("mfdbatu %0,0" : "=r" (dbat0u));
__asm volatile ("mfdbatl %0,0" : "=r" (dbat0l));
__asm volatile ("mfibatu %0,0" : "=r" (ibat0u));
__asm volatile ("mfibatl %0,0" : "=r" (ibat0l));
__asm volatile ("mfdbatu %0,1" : "=r" (dbat1u));
__asm volatile ("mfdbatl %0,1" : "=r" (dbat1l));
__asm volatile ("mfibatu %0,1" : "=r" (ibat1u));
__asm volatile ("mfibatl %0,1" : "=r" (ibat1l));
__asm volatile ("mfdbatu %0,2" : "=r" (dbat2u));
__asm volatile ("mfdbatl %0,2" : "=r" (dbat2l));
__asm volatile ("mfibatu %0,2" : "=r" (ibat2u));
__asm volatile ("mfibatl %0,2" : "=r" (ibat2l));
__asm volatile ("mfdbatu %0,3" : "=r" (dbat3u));
__asm volatile ("mfdbatl %0,3" : "=r" (dbat3l));
__asm volatile ("mfibatu %0,3" : "=r" (ibat3u));
__asm volatile ("mfibatl %0,3" : "=r" (ibat3l));
__asm volatile ("mfmsr %0" : "=r" (msr));
__asm volatile ("mfspr %0,1008": "=r" (hid0));
__asm volatile ("mfspr %0,1017": "=r" (l2cr_reg));
printf("dbat0u: %08x dbat0l: %08x ibat0u: %08x ibat0l: %08x\n",
dbat0u, dbat0l, ibat0u, ibat0l);
printf("dbat1u: %08x dbat1l: %08x ibat1u: %08x ibat1l: %08x\n",
dbat1u, dbat1l, ibat1u, ibat1l);
printf("dbat2u: %08x dbat2l: %08x ibat2u: %08x ibat2l: %08x\n",
dbat2u, dbat2l, ibat2u, ibat2l);
printf("dbat3u: %08x dbat3l: %08x ibat3u: %08x ibat3l: %08x\n",
dbat3u, dbat3l, ibat3u, ibat3l);
printf("\nMSR: %08x HID0: %08x L2CR: %08x \n", msr,hid0, l2cr_reg);
}
void remove_init_data(void)
{
char *s;
/* Invalidate and disable data cache */
invalidate_l1_data_cache();
dcache_disable();
s = getenv("x86_cache");
if (!s)
{
icache_enable();
dcache_enable();
}
else if (s)
{
if (strcmp(s, "dcache")==0)
{
dcache_enable();
}
else if (strcmp(s, "icache") == 0)
{
icache_enable();
}
else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0)
{
dcache_enable();
icache_enable();
}
}
/* show_bat_mapping();*/
}
#ifndef GLUE_H
#define GLUE_H
typedef unsigned int pci_dev_t;
int mypci_find_device(int vendor, int product, int index);
int mypci_bus(int device);
int mypci_devfn(int device);
unsigned long get_bar_size(pci_dev_t dev, int offset);
u8 mypci_read_cfg_byte(int bus, int devfn, int offset);
u16 mypci_read_cfg_word(int bus, int devfn, int offset);
u32 mypci_read_cfg_long(int bus, int devfn, int offset);
void mypci_write_cfg_byte(int bus, int devfn, int offset, u8 value);
void mypci_write_cfg_word(int bus, int devfn, int offset, u16 value);
void mypci_write_cfg_long(int bus, int devfn, int offset, u32 value);
void _printf(const char *fmt, ...);
char *_getenv(char *name);
void *malloc(size_t size);
void memset(void *addr, int value, size_t size);
void memcpy(void *to, void *from, size_t numbytes);
int strcmp(char *, char *);
void enable_compatibility_hole(void);
void disable_compatibility_hole(void);
void map_rom(pci_dev_t dev, unsigned long address);
void unmap_rom(pci_dev_t dev);
int attempt_map_rom(pci_dev_t dev, void *copy_address);
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_BUS(d) (((d) >> 16) & 0xff)
#define PCI_DEV(d) (((d) >> 11) & 0x1f)
#define PCI_FUNC(d) (((d) >> 8) & 0x7)
#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
#define PCI_ANY_ID (~0)
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
#define OFF(addr) ((addr) & 0xFFFF)
#define SEG(addr) (((addr)>>4) &0xF000)
#endif
@echo off
REM Setup for compiling with Borland C++ 3.1.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC3;%BC3_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC3;%BC3_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC3_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC3.MK
SET USE_DPMI16=
SET USE_WIN16=
SET USE_WIN32=
SET USE_SNAP=
PATH %SCITECH_BIN%;%BC3_PATH%\BIN;%DEFPATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC3_PATH%\BIN\turboc.cfg
echo -L%LIB% >> %BC3_PATH%\BIN\turboc.cfg
echo -L%LIB% > %BC3_PATH%\BIN\tlink.cfg
echo Borland C++ 3.1 DOS compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_WIN16=
SET USE_WIN32=1
SET USE_VXD=
SET USE_TNT=
SET USE_BC5=
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC4
PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM: Enable Win32 SDK if desired (sdk on command line)
if NOT .%1%==.sdk goto createfiles
call win32sdk.bat borland
:createfiles
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
echo Borland C++ 4.5 32 bit Windows compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 4.5 in 16 bit mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC4;%BC4_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC4;%BC4_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
SET USE_DPMI16=
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_BC5=
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC4
PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg
echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg
echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg
echo Borland C++ 4.5 16 bit DOS compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 4.5 in 32 bit mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_DPMI16=
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_TNT=
SET USE_BC5=
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC4
PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
echo Borland C++ 4.5 32 bit DOS compilation configuration set up (DPMI32).
@echo off
REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC4;%BC4_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC4;%BC4_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_TNT=
SET USE_BC5=
SET WIN32_GUI=
SET USE_SNAP=1
SET BC_LIBBASE=BC4
PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
echo Borland C++ 4.5 Snap compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 4.5 in 32 bit mode with Phar Lap TNT
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_DPMI16=
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_TNT=1
SET USE_BC5=
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC4
PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM If you set the following to a 1, a TNT DosStyle app will be created.
REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
REM run under real DOS when using our libraries, since we require access
REM to functions that the Win32 API does not support (such as direct access
REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
REM work too well).
REM
REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
REM and hence will never be able to run under Win95 or WinNT, only DOS.
SET DOSSTYLE=
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
echo Borland C++ 4.5 32 bit DOS compilation configuration set up (TNT).
@echo off
REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows VxD mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC4;%BC4_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC4;%BC4_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=1
SET USE_TNT=
SET USE_BC5=
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC4
PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
echo Borland C++ 4.5 32-bit VxD compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 4.5 in 16 bit Windows mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC4;%BC4_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC4;%BC4_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
SET USE_DPMI16=
SET USE_WIN16=1
SET USE_WIN32=
SET USE_VXD=
SET USE_BC5=
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC4
PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg
echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg
echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg
echo Borland C++ 4.5 16 bit Windows compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_WIN16=
SET USE_WIN32=1
SET USE_VXD=
SET USE_TNT=
SET USE_BC5=
SET WIN32_GUI=1
SET USE_SNAP=
SET BC_LIBBASE=BC4
PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM: Enable Win32 SDK if desired (sdk on command line)
if NOT .%1%==.sdk goto createfiles
call win32sdk.bat borland
:createfiles
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
echo Borland C++ 4.5 32 bit Windows compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET C_INCLUDE=%BC5_PATH%\INCLUDE
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_WIN16=
SET USE_WIN32=1
SET USE_VXD=
SET USE_TNT=
SET USE_SMX32=
SET USE_SMX16=
SET USE_BC5=1
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC5
PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
REM: Enable Win32 SDK if desired (sdk on command line)
if NOT .%1%==.sdk goto createfiles
call win32sdk.bat borland
:createfiles
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
echo Borland C++ 5.0 32 bit Windows compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 5.0 in 16 bit mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC5;%BC5_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC5;%BC5_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
SET USE_DPMI16=
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_SMX32=
SET USE_SMX16=
SET USE_BC5=1
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC5
PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg
echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg
echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg
echo Borland C++ 5.0 16 bit DOS compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 5.0 in 32 bit mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_DPMI16=
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_TNT=
SET USE_SMX32=
SET USE_SMX16=
SET USE_BC5=1
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC5
PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
echo Borland C++ 5.0 32 bit DOS compilation configuration set up (DPMI32).
@echo off
REM Setup for compiling with Borland C++ 5.0 in 32 bit mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BC5;%BC5_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BC5;%BC5_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_DPMI16=
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_TNT=
SET USE_SMX32=1
SET USE_SMX16=
SET USE_BC5=1
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC5
PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
echo Borland C++ 5.0 32 bit SMX compilation configuration set up (SMX32).
@echo off
REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC5;%BC5_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC5;%BC5_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_TNT=
SET USE_SMX32=
SET USE_SMX16=
SET USE_BC5=1
SET WIN32_GUI=
SET USE_SNAP=1
SET BC_LIBBASE=BC5
PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
echo Borland C++ 5.0 Snap compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 5.0 in 32 bit mode with Phar Lap TNT
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_DPMI16=
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=
SET USE_TNT=1
SET USE_SMX32=
SET USE_SMX16=
SET USE_BC5=1
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC5
PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
REM If you set the following to a 1, a TNT DosStyle app will be created.
REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
REM run under real DOS when using our libraries, since we require access
REM to functions that the Win32 API does not support (such as direct access
REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
REM work too well).
REM
REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
REM and hence will never be able to run under Win95 or WinNT, only DOS.
SET DOSSTYLE=
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
echo Borland C++ 5.0 32 bit DOS compilation configuration set up (TNT).
@echo off
REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC5;%BC5_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC5;%BC5_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
SET USE_WIN16=
SET USE_WIN32=
SET USE_VXD=1
SET USE_TNT=
SET USE_SMX32=
SET USE_SMX16=
SET USE_BC5=1
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC5
PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
echo Borland C++ 5.0 32 bit Windows (VxD) compilation configuration set up.
@echo off
REM Setup for compiling with Borland C++ 5.0 in 16 bit Windows mode.
if .%CHECKED%==.1 goto checked_build
SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC5;%BC5_PATH%\LIB;.
echo Release build enabled.
goto setvars
:checked_build
SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC5;%BC5_PATH%\LIB;.
echo Checked debug build enabled.
goto setvars
:setvars
SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
SET USE_DPMI16=
SET USE_WIN16=1
SET USE_WIN32=
SET USE_VXD=
SET USE_BC5=1
SET USE_SMX32=
SET USE_SMX16=
SET WIN32_GUI=
SET USE_SNAP=
SET BC_LIBBASE=BC5
PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
REM: Create Borland compile/link configuration scripts
echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg
echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg
echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg
echo Borland C++ 5.0 16 bit Windows compilation configuration set up.
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment