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Commit 21a257b9 authored by Zhichun Hua's avatar Zhichun Hua Committed by York Sun
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armv8: Fix TCR macros for shareability attribute


For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.

Signed-off-by: default avatarZhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
parent 25195600
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