armv8: ls1046aqds: Adjust IFC timing for NOR flash

Increase setup, assertion and hold time related to chip-select signal.
Additional delay is needed for the signal to propogate through FPGA.
This adjustment slightly increase the read and write cycle but has no
impact on burst read or write.

Signed-off-by: York Sun <york.sun@nxp.com>

include/configs/ls1046aqds.h

@@ -176,12 +176,13 @@ unsigned long get_board_ddr_clk(void);
 					CSOR_NOR_TRHZ_80)
 #define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
 					FTIM0_NOR_TEADC(0x5) | \
+					FTIM0_NOR_TAVDS(0x6) | \
 					FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
 					FTIM1_NOR_TRAD_NOR(0x1a) | \
 					FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
-					FTIM2_NOR_TCH(0x4) | \
+#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x8) | \
+					FTIM2_NOR_TCH(0x8) | \
 					FTIM2_NOR_TWPH(0xe) | \
 					FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3		0