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Commit 1860d101 authored by Lokesh Vutla's avatar Lokesh Vutla Committed by Tom Rini
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ARM: DRA7-evm: DDR3: Update leveling values 


Update the software leveling parameters.
This fixes the random crash seen on DRA7-evm.

Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
parent 802bb57a
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arch/arm/cpu/armv7/omap5/sdram.c
+ 30
− 30
View file @ 1860d101
...@@ -152,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { ...@@ -152,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A, .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A, .emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB, .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB, .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_lvl_ctl = 0x00000000,
...@@ -177,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { ...@@ -177,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A, .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A, .emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB, .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB, .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_lvl_ctl = 0x00000000,
...@@ -423,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { ...@@ -423,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32 const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
0x00BB00BB, 0x00980098,
0x00440044, 0x00340034,
0x00440044, 0x00350035,
0x00440044, 0x00340034,
0x00440044, 0x00310031,
0x00440044, 0x00340034,
0x007F007F, 0x007F007F,
0x007F007F, 0x007F007F,
0x007F007F, 0x007F007F,
0x007F007F, 0x007F007F,
0x007F007F, 0x007F007F,
0x00600060, 0x00480048,
0x00600060, 0x004A004A,
0x00600060, 0x00520052,
0x00600060, 0x00550055,
0x00600060, 0x00500050,
0x00000000, 0x00000000,
0x00600020, 0x00600020,
0x40010080, 0x40010080,
...@@ -452,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { ...@@ -452,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
const u32 const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x00BB00BB, 0x00980098,
0x00440044, 0x00330033,
0x00440044, 0x00330033,
0x00440044, 0x002F002F,
0x00440044, 0x00320032,
0x00440044, 0x00310031,
0x007F007F, 0x007F007F,
0x007F007F, 0x007F007F,
0x007F007F, 0x007F007F,
0x007F007F, 0x007F007F,
0x007F007F, 0x007F007F,
0x00600060, 0x00520052,
0x00600060, 0x00520052,
0x00600060, 0x00470047,
0x00600060, 0x00490049,
0x00600060, 0x00500050,
0x00000000, 0x00000000,
0x00600020, 0x00600020,
0x40010080, 0x40010080,
......
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