ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devices

Zynq 7000S (Single A9 core) devices is using different ID code.
This patch adds this new codes and assign them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

board/xilinx/zynq/board.c

@@ -19,7 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 static xilinx_desc fpga;
 
 /* It can be done differently */
+static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
+static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
@@ -37,9 +40,18 @@ int board_init(void)
 	idcode = zynq_slcr_get_idcode();
 
 	switch (idcode) {
+	case XILINX_ZYNQ_7007S:
+		fpga = fpga007s;
+		break;
 	case XILINX_ZYNQ_7010:
 		fpga = fpga010;
 		break;
+	case XILINX_ZYNQ_7012S:
+		fpga = fpga012s;
+		break;
+	case XILINX_ZYNQ_7014S:
+		fpga = fpga014s;
+		break;
 	case XILINX_ZYNQ_7015:
 		fpga = fpga015;
 		break;

include/zynqpl.h

@@ -19,7 +19,10 @@ extern struct xilinx_fpga_op zynq_op;
 # define FPGA_ZYNQPL_OPS	NULL
 #endif
 
+#define XILINX_ZYNQ_7007S	0x3
 #define XILINX_ZYNQ_7010	0x2
+#define XILINX_ZYNQ_7012S	0x1c
+#define XILINX_ZYNQ_7014S	0x8
 #define XILINX_ZYNQ_7015	0x1b
 #define XILINX_ZYNQ_7020	0x7
 #define XILINX_ZYNQ_7030	0xc
@@ -28,7 +31,10 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_ZYNQ_7100	0x16
 
 /* Device Image Sizes */
+#define XILINX_XC7Z007S_SIZE	16669920/8
 #define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z012S_SIZE	28085344/8
+#define XILINX_XC7Z014S_SIZE	32364512/8
 #define XILINX_XC7Z015_SIZE	28085344/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
@@ -37,10 +43,22 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_XC7Z100_SIZE	139330784/8
 
 /* Descriptor Macros */
+#define XILINX_XC7Z007S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z007s" }
+
 #define XILINX_XC7Z010_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
 	"7z010" }
 
+#define XILINX_XC7Z012S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z012s" }
+
+#define XILINX_XC7Z014S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z014s" }
+
 #define XILINX_XC7Z015_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
 	"7z015" }