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    • Forked from Reform / reform-boundary-uboot
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    • Paul Burton's avatar
      c5bf161f
      Update Paul Burton's email address · c5bf161f
      Paul Burton authored 
      
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.

Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
      c5bf161f
      History
      Update Paul Burton's email address
      Paul Burton authored 
      
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.

Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
    cob.cfg 1.26 KiB 
    /*
 * Copyright (C) 2013 Boundary Devices
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Refer doc/README.imximage for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */

/* image version */
IMAGE_VERSION 2

/*
 * Boot Device : one of
 * spi, sd (the board has no nand neither onenand)
 */
BOOT_FROM      spi

#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"

/* NC YET */
#define MX6_MMDC_P0_MPDGCTRL0_VAL	0x42720306
#define MX6_MMDC_P0_MPDGCTRL1_VAL	0x026F0266
#define MX6_MMDC_P1_MPDGCTRL0_VAL	0x4273030A
#define MX6_MMDC_P1_MPDGCTRL1_VAL	0x02740240
#define MX6_MMDC_P0_MPRDDLCTL_VAL	0x45393B3E
#define MX6_MMDC_P1_MPRDDLCTL_VAL	0x403A3747
#define MX6_MMDC_P0_MPWRDLCTL_VAL	0x40434541
#define MX6_MMDC_P1_MPWRDLCTL_VAL	0x473E4A3B
#define MX6_MMDC_P0_MPWLDECTRL0_VAL	0x0011000E
#define MX6_MMDC_P0_MPWLDECTRL1_VAL	0x000E001B
#define MX6_MMDC_P1_MPWLDECTRL0_VAL	0x00190015
#define MX6_MMDC_P1_MPWLDECTRL1_VAL	0x00070018
#define WALAT	0

#include "../common/mx6/ddr-setup.cfg"
#define RANK 0
#define BUS_WIDTH 64
/* MT41K128M16JT-125 IT:K */
#include "../common/mx6/1066mhz_128mx16.cfg"
#include "../common/mx6/clocks.cfg"