Skip to content
Snippets Groups Projects
Select Git revision
  • ea9f6bce383cc9fbcdee28b5836109b1a6dba574
  • master default protected
  • early-display
  • variant-emmc-nvme-boot
  • 2023-01-25
  • v3
  • variant-emmc-nvme-boot
  • 2020-06-01
8 results

sdram.c

Blame
  • Forked from Reform / reform-boundary-uboot
    Source project has a limited visibility.
    sdram.c 17.20 KiB
    /*
     * (C) Copyright 2006
     * Sylvie Gohl,		    AMCC/IBM, gohl.sylvie@fr.ibm.com
     * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
     * Thierry Roman,	    AMCC/IBM, thierry_roman@fr.ibm.com
     * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
     * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
     *
     * (C) Copyright 2007
     * Stefan Roese, DENX Software Engineering, sr@denx.de.
     *
     * This program is free software; you can redistribute it and/or
     * modify it under the terms of the GNU General Public License as
     * published by the Free Software Foundation; either version 2 of
     * the License, or (at your option) any later version.
     *
     * This program is distributed in the hope that it will be useful,
     * but WITHOUT ANY WARRANTY; without even the implied warranty of
     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     * GNU General Public License for more details.
     *
     * You should have received a copy of the GNU General Public License
     * along with this program; if not, write to the Free Software
     * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     * MA 02111-1307 USA
     */
    
    /* define DEBUG for debugging output (obviously ;-)) */
    #if 0
    #define DEBUG
    #endif
    
    #include <common.h>
    #include <asm/processor.h>
    #include <asm/mmu.h>
    #include <asm/io.h>
    #include <ppc440.h>
    
    #include "sdram.h"
    
    /*
     * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
     * region. Right now the cache should still be disabled in U-Boot because of the
     * EMAC driver, that need it's buffer descriptor to be located in non cached
     * memory.
     *
     * If at some time this restriction doesn't apply anymore, just define
     * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
     * everything correctly.
     */
    #ifdef CFG_ENABLE_SDRAM_CACHE
    #define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
    #else
    #define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
    #endif
    
    void dcbz_area(u32 start_address, u32 num_bytes);
    void dflush(void);
    
    #ifdef CONFIG_ADD_RAM_INFO
    static u32 is_ecc_enabled(void)
    {
    	u32 val;
    
    	mfsdram(DDR0_22, val);
    	val &= DDR0_22_CTRL_RAW_MASK;
    	if (val)
    		return 1;
    	else
    		return 0;