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  • 2020-06-01
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emif.h

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  • Forked from Reform / reform-boundary-uboot
    5152 commits behind the upstream repository.
    • Jyri Sarha's avatar
      8c17cbdf
      arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm · 8c17cbdf
      Jyri Sarha authored
      
      Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
      and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
      the default values LCDC suffers from DMA FIFO underflows and frame
      synchronization lost errors. The initialization values are the highest
      that work flawlessly when heavy memory load is generated by CPU. 32bpp
      colors were used in the test. On BBB the video mode used 110MHz pixel
      clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
      clock.
      
      Signed-off-by: default avatarJyri Sarha <jsarha@ti.com>
      Reviewed-by: default avatarTom Rini <trini@konsulko.com>
      8c17cbdf
      History
      arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
      Jyri Sarha authored
      
      Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
      and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
      the default values LCDC suffers from DMA FIFO underflows and frame
      synchronization lost errors. The initialization values are the highest
      that work flawlessly when heavy memory load is generated by CPU. 32bpp
      colors were used in the test. On BBB the video mode used 110MHz pixel
      clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
      clock.
      
      Signed-off-by: default avatarJyri Sarha <jsarha@ti.com>
      Reviewed-by: default avatarTom Rini <trini@konsulko.com>
    emif.h 38.17 KiB