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processor.h

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  • Forked from Reform / reform-boundary-uboot
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    • York Sun's avatar
      d2404141
      powerpc/mpc85xx: Add B4860 and variant SoCs · d2404141
      York Sun authored
      
      Add support for Freescale B4860 and variant SoCs. Features of B4860 are
      (incomplete list):
      
      Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
          clusters-each core runs up to 1.2 GHz, with an architecture highly
          optimized for wireless base station applications
      Four dual-thread e6500 Power Architecture processors organized in one
          cluster-each core runs up to 1.8 GHz
      Two DDR3/3L controllers for high-speed, industry-standard memory interface
          each runs at up to 1866.67 MHz
      MAPLE-B3 hardware acceleration-for forward error correction schemes
          including Turbo or Viterbi decoding, Turbo encoding and rate matching,
          MIMO MMSE equalization scheme, matrix operations, CRC insertion and
          check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
          and UMTS chip rate acceleration
      CoreNet fabric that fully supports coherency using MESI protocol between
          the e6500 cores, SC3900 FVP cores, memories and external interfaces.
          CoreNet fabric interconnect runs at 667 MHz and supports coherent and
          non-coherent out of order transactions with prioritization and
          bandwidth allocation amongst CoreNet endpoints.
      Data Path Acceleration Architecture, which includes the following:
        Frame Manager (FMan), which supports in-line packet parsing and general
          classification to enable policing and QoS-based packet distribution
        Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
          of queue management, task management, load distribution, flow ordering,
          buffer management, and allocation tasks from the cores
        Security engine (SEC 5.3)-crypto-acceleration for protocols such as
          IPsec, SSL, and 802.16
        RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
          outbound). Supports types 5, 6 (outbound only)
      Large internal cache memory with snooping and stashing capabilities for
          bandwidth saving and high utilization of processor elements. The
          9856-Kbyte internal memory space includes the following:
        32 Kbyte L1 ICache per e6500/SC3900 core
        32 Kbyte L1 DCache per e6500/SC3900 core
        2048 Kbyte unified L2 cache for each SC3900 FVP cluster
        2048 Kbyte unified L2 cache for the e6500 cluster
        Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
      Sixteen 10-GHz SerDes lanes serving:
        Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
          of up to 8 lanes
        Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
          less antenna connection
        Two 10-Gbit Ethernet controllers (10GEC)
        Six 1G/2.5-Gbit Ethernet controllers for network communications
        PCI Express controller
        Debug (Aurora)
      Two OCeaN DMAs
      Various system peripherals
      182 32-bit timers
      
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      d2404141
      History
      powerpc/mpc85xx: Add B4860 and variant SoCs
      York Sun authored
      
      Add support for Freescale B4860 and variant SoCs. Features of B4860 are
      (incomplete list):
      
      Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
          clusters-each core runs up to 1.2 GHz, with an architecture highly
          optimized for wireless base station applications
      Four dual-thread e6500 Power Architecture processors organized in one
          cluster-each core runs up to 1.8 GHz
      Two DDR3/3L controllers for high-speed, industry-standard memory interface
          each runs at up to 1866.67 MHz
      MAPLE-B3 hardware acceleration-for forward error correction schemes
          including Turbo or Viterbi decoding, Turbo encoding and rate matching,
          MIMO MMSE equalization scheme, matrix operations, CRC insertion and
          check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
          and UMTS chip rate acceleration
      CoreNet fabric that fully supports coherency using MESI protocol between
          the e6500 cores, SC3900 FVP cores, memories and external interfaces.
          CoreNet fabric interconnect runs at 667 MHz and supports coherent and
          non-coherent out of order transactions with prioritization and
          bandwidth allocation amongst CoreNet endpoints.
      Data Path Acceleration Architecture, which includes the following:
        Frame Manager (FMan), which supports in-line packet parsing and general
          classification to enable policing and QoS-based packet distribution
        Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
          of queue management, task management, load distribution, flow ordering,
          buffer management, and allocation tasks from the cores
        Security engine (SEC 5.3)-crypto-acceleration for protocols such as
          IPsec, SSL, and 802.16
        RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
          outbound). Supports types 5, 6 (outbound only)
      Large internal cache memory with snooping and stashing capabilities for
          bandwidth saving and high utilization of processor elements. The
          9856-Kbyte internal memory space includes the following:
        32 Kbyte L1 ICache per e6500/SC3900 core
        32 Kbyte L1 DCache per e6500/SC3900 core
        2048 Kbyte unified L2 cache for each SC3900 FVP cluster
        2048 Kbyte unified L2 cache for the e6500 cluster
        Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
      Sixteen 10-GHz SerDes lanes serving:
        Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
          of up to 8 lanes
        Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
          less antenna connection
        Two 10-Gbit Ethernet controllers (10GEC)
        Six 1G/2.5-Gbit Ethernet controllers for network communications
        PCI Express controller
        Debug (Aurora)
      Two OCeaN DMAs
      Various system peripherals
      182 32-bit timers
      
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
    phy.c 16.80 KiB
    /*
     * Generic PHY Management code
     *
     * This program is free software; you can redistribute it and/or
     * modify it under the terms of the GNU General Public License as
     * published by the Free Software Foundation; either version 2 of
     * the License, or (at your option) any later version.
     *
     * This program is distributed in the hope that it will be useful,
     * but WITHOUT ANY WARRANTY; without even the implied warranty of
     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     * GNU General Public License for more details.
     *
     * You should have received a copy of the GNU General Public License
     * along with this program; if not, write to the Free Software
     * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     * MA 02111-1307 USA
     *
     *
     * Copyright 2011 Freescale Semiconductor, Inc.
     * author Andy Fleming
     *
     * Based loosely off of Linux's PHY Lib
     */
    
    #include <config.h>
    #include <common.h>
    #include <malloc.h>
    #include <net.h>
    #include <command.h>
    #include <miiphy.h>
    #include <phy.h>
    #include <errno.h>
    
    /* Generic PHY support and helper functions */
    
    /**
     * genphy_config_advert - sanitize and advertise auto-negotation parameters
     * @phydev: target phy_device struct
     *
     * Description: Writes MII_ADVERTISE with the appropriate values,
     *   after sanitizing the values to make sure we only advertise
     *   what is supported.  Returns < 0 on error, 0 if the PHY's advertisement
     *   hasn't changed, and > 0 if it has changed.
     */
    int genphy_config_advert(struct phy_device *phydev)
    {
    	u32 advertise;
    	int oldadv, adv;
    	int err, changed = 0;
    
    	/* Only allow advertising what
    	 * this PHY supports */
    	phydev->advertising &= phydev->supported;
    	advertise = phydev->advertising;
    
    	/* Setup standard advertisement */
    	oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
    
    	if (adv < 0)
    		return adv;
    
    	adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
    		 ADVERTISE_PAUSE_ASYM);
    	if (advertise & ADVERTISED_10baseT_Half)
    		adv |= ADVERTISE_10HALF;
    	if (advertise & ADVERTISED_10baseT_Full)
    		adv |= ADVERTISE_10FULL;
    	if (advertise & ADVERTISED_100baseT_Half)
    		adv |= ADVERTISE_100HALF;