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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
Wolfgang Denk authoredSigned-off-by:
Wolfgang Denk <wd@denx.de>
zynqpl.c 12.00 KiB
/*
* (C) Copyright 2012-2013, Xilinx, Michal Simek
*
* (C) Copyright 2012
* Joe Hershberger <joe.hershberger@ni.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <fs.h>
#include <zynqpl.h>
#include <linux/sizes.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
#define DEVCFG_ISR_DMA_DONE 0x00002000
#define DEVCFG_ISR_PCFG_DONE 0x00000004
#define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
#define DEVCFG_STATUS_PCFG_INIT 0x00000010
#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
#ifndef CONFIG_SYS_FPGA_WAIT
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
#ifndef CONFIG_SYS_FPGA_PROG_TIME
#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif
static int zynq_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
#define DUMMY_WORD 0xffffffff
/* Xilinx binary format header */
static const u32 bin_format[] = {
DUMMY_WORD, /* Dummy words */
DUMMY_WORD,
DUMMY_WORD,
DUMMY_WORD,
DUMMY_WORD,
DUMMY_WORD,
DUMMY_WORD,
DUMMY_WORD,
0x000000bb, /* Sync word */
0x11220044, /* Sync word */
DUMMY_WORD,
DUMMY_WORD,
0xaa995566, /* Sync word */
};
#define SWAP_NO 1
#define SWAP_DONE 2
/*
* Load the whole word from unaligned buffer
* Keep in your mind that it is byte loading on little-endian system
*/