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    c6d4705f
    x86: quark: Configure MTRR to enable cache · c6d4705f
    Bin Meng authored
    
    Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
    are accessed indirectly via the message port and not the traditional
    MSR mechanism. Only UC, WT and WB cache types are supported.
    
    We configure all the fixed range MTRRs with common values (VGA RAM
    as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
    WB, which significantly improves the boot time performance.
    
    With this commit, it takes only 2 seconds for U-Boot to boot to shell
    on Intel Galileo board. Previously it took about 6 seconds.
    
    Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
    Acked-by: default avatarSimon Glass <sjg@chromium.org>
    Tested-by: default avatarSimon Glass <sjg@chromium.org>
    c6d4705f
    History
    x86: quark: Configure MTRR to enable cache
    Bin Meng authored
    
    Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
    are accessed indirectly via the message port and not the traditional
    MSR mechanism. Only UC, WT and WB cache types are supported.
    
    We configure all the fixed range MTRRs with common values (VGA RAM
    as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
    WB, which significantly improves the boot time performance.
    
    With this commit, it takes only 2 seconds for U-Boot to boot to shell
    on Intel Galileo board. Previously it took about 6 seconds.
    
    Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
    Acked-by: default avatarSimon Glass <sjg@chromium.org>
    Tested-by: default avatarSimon Glass <sjg@chromium.org>