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ddr.c
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Reform / reform-boundary-uboot
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Eric Nelson authored
The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by:
Eric Nelson <eric@nelint.com> Reviewed-by:
Marek Vasut <marex@denx.de>
Eric Nelson authoredThe DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by:
