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fsl_ddr_gen4.c
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Shengzhou Liu authored
During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
Shengzhou Liu authoredDuring DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by:
