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designware.c
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Armando Visconti authored
This patch solves a TX/RX problem which happens at 10Mbps, due to the fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between two consecutive writes on the same register. Signed-off-by:
Armando Visconti <armando.visconti@st.com> Signed-off-by:
Amit Virdi <amit.virdi@st.com>
Armando Visconti authoredThis patch solves a TX/RX problem which happens at 10Mbps, due to the fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between two consecutive writes on the same register. Signed-off-by:
