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processor.h

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    • York Sun's avatar
      9e758758
      powerpc/mpc85xx: Add T4240 SoC · 9e758758
      York Sun authored
      
      Add support for Freescale T4240 SoC. Feature of T4240 are
      (incomplete list):
      
      12 dual-threaded e6500 cores built on Power Architecture® technology
        Arranged as clusters of four cores sharing a 2 MB L2 cache.
        Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
          v2.06-compliant)
        Three levels of instruction: user, supervisor, and hypervisor
      1.5 MB CoreNet Platform Cache (CPC)
      Hierarchical interconnect fabric
        CoreNet fabric supporting coherent and non-coherent transactions with
          prioritization and bandwidth allocation amongst CoreNet end-points
        1.6 Tbps coherent read bandwidth
        Queue Manager (QMan) fabric supporting packet-level queue management and
          quality of service scheduling
      Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
          support
        Memory prefetch engine (PMan)
      Data Path Acceleration Architecture (DPAA) incorporating acceleration for
          the following functions:
        Packet parsing, classification, and distribution (Frame Manager 1.1)
        Queue management for scheduling, packet sequencing, and congestion
          management (Queue Manager 1.1)
        Hardware buffer management for buffer allocation and de-allocation
          (BMan 1.1)
        Cryptography acceleration (SEC 5.0) at up to 40 Gbps
        RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
        Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
        DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
      32 SerDes lanes at up to 10.3125 GHz
      Ethernet interfaces
        Up to four 10 Gbps Ethernet MACs
        Up to sixteen 1 Gbps Ethernet MACs
        Maximum configuration of 4 x 10 GE + 8 x 1 GE
      High-speed peripheral interfaces
        Four PCI Express 2.0/3.0 controllers
        Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
          Type 11 messaging and Type 9 data streaming support
        Interlaken look-aside interface for serial TCAM connection
      Additional peripheral interfaces
        Two serial ATA (SATA 2.0) controllers
        Two high-speed USB 2.0 controllers with integrated PHY
        Enhanced secure digital host controller (SD/MMC/eMMC)
        Enhanced serial peripheral interface (eSPI)
        Four I2C controllers
        Four 2-pin or two 4-pin UARTs
        Integrated Flash controller supporting NAND and NOR flash
      Two eight-channel DMA engines
      Support for hardware virtualization and partitioning enforcement
      QorIQ Platform's Trust Architecture 1.1
      
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      9e758758
      History
      powerpc/mpc85xx: Add T4240 SoC
      York Sun authored
      
      Add support for Freescale T4240 SoC. Feature of T4240 are
      (incomplete list):
      
      12 dual-threaded e6500 cores built on Power Architecture® technology
        Arranged as clusters of four cores sharing a 2 MB L2 cache.
        Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
          v2.06-compliant)
        Three levels of instruction: user, supervisor, and hypervisor
      1.5 MB CoreNet Platform Cache (CPC)
      Hierarchical interconnect fabric
        CoreNet fabric supporting coherent and non-coherent transactions with
          prioritization and bandwidth allocation amongst CoreNet end-points
        1.6 Tbps coherent read bandwidth
        Queue Manager (QMan) fabric supporting packet-level queue management and
          quality of service scheduling
      Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
          support
        Memory prefetch engine (PMan)
      Data Path Acceleration Architecture (DPAA) incorporating acceleration for
          the following functions:
        Packet parsing, classification, and distribution (Frame Manager 1.1)
        Queue management for scheduling, packet sequencing, and congestion
          management (Queue Manager 1.1)
        Hardware buffer management for buffer allocation and de-allocation
          (BMan 1.1)
        Cryptography acceleration (SEC 5.0) at up to 40 Gbps
        RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
        Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
        DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
      32 SerDes lanes at up to 10.3125 GHz
      Ethernet interfaces
        Up to four 10 Gbps Ethernet MACs
        Up to sixteen 1 Gbps Ethernet MACs
        Maximum configuration of 4 x 10 GE + 8 x 1 GE
      High-speed peripheral interfaces
        Four PCI Express 2.0/3.0 controllers
        Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
          Type 11 messaging and Type 9 data streaming support
        Interlaken look-aside interface for serial TCAM connection
      Additional peripheral interfaces
        Two serial ATA (SATA 2.0) controllers
        Two high-speed USB 2.0 controllers with integrated PHY
        Enhanced secure digital host controller (SD/MMC/eMMC)
        Enhanced serial peripheral interface (eSPI)
        Four I2C controllers
        Four 2-pin or two 4-pin UARTs
        Integrated Flash controller supporting NAND and NOR flash
      Two eight-channel DMA engines
      Support for hardware virtualization and partitioning enforcement
      QorIQ Platform's Trust Architecture 1.1
      
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>