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Andy Fleming authored
SOFT_RESET must be asserted for at least 3 TX clocks. Usually, that's about 30 clock cycles, so it's been mostly working. But we had no guarantee, and at slower bitrates, it's just over a microsecond (over 1000 clock cycles). This enforces a 2 microsecond gap between assertion and deassertion. Signed-off-by:
Andy Fleming <afleming@freescale.com> Signed-off-by:
Ben Warren <biggerbadderben@gmail.com>
Andy Fleming authoredSOFT_RESET must be asserted for at least 3 TX clocks. Usually, that's about 30 clock cycles, so it's been mostly working. But we had no guarantee, and at slower bitrates, it's just over a microsecond (over 1000 clock cycles). This enforces a 2 microsecond gap between assertion and deassertion. Signed-off-by:
Andy Fleming <afleming@freescale.com> Signed-off-by:
Ben Warren <biggerbadderben@gmail.com>