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spi_flash.c

Forked from Reform / reform-boundary-uboot
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  • Cyrille Pitchen's avatar
    9bcb0188
    Revert "sf: Fix quad bit set for micron devices" · 9bcb0188
    Cyrille Pitchen authored
    
    This reverts commit c56ae751.
    
    Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
    Configuration Register (EVCR), Micron memories expect ALL commands to use
    the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
    accepted.
    
    Within the reverted commit, the write_evcr() function is implemented using
    the spi_flash_write_common(), which is a shortcut for the
    [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(),
    spi_flash_cmd_wait_ready() ] sequence.
    
    Since the internal state of the Micron memory has been changed when the
    spi_flash_cmd_write() function completes, the later call of the
    spi_flash_cmd_wait_ready() function fails.
    
    Indeed the SPI controller driver is not aware of the SPI protocol switch.
    
    Further patches will fix the support of Micron QSPI memories.
    
    Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
    [Rebase on master, use JEDEC_MFR(info) in place of idcode0]
    Signed-off-by: default avatarJagan Teki <jagan@openedev.com>
    9bcb0188
    History
    Revert "sf: Fix quad bit set for micron devices"
    Cyrille Pitchen authored
    
    This reverts commit c56ae751.
    
    Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
    Configuration Register (EVCR), Micron memories expect ALL commands to use
    the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
    accepted.
    
    Within the reverted commit, the write_evcr() function is implemented using
    the spi_flash_write_common(), which is a shortcut for the
    [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(),
    spi_flash_cmd_wait_ready() ] sequence.
    
    Since the internal state of the Micron memory has been changed when the
    spi_flash_cmd_write() function completes, the later call of the
    spi_flash_cmd_wait_ready() function fails.
    
    Indeed the SPI controller driver is not aware of the SPI protocol switch.
    
    Further patches will fix the support of Micron QSPI memories.
    
    Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
    [Rebase on master, use JEDEC_MFR(info) in place of idcode0]
    Signed-off-by: default avatarJagan Teki <jagan@openedev.com>