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York Sun authored
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by:
York Sun <yorksun@freescale.com>
York Sun authoredErratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by:
York Sun <yorksun@freescale.com>