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fsl_ddr_gen4.c
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Shengzhou Liu authored
During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by:
York Sun <york.sun@nxp.com>
Shengzhou Liu authoredDuring the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by:
York Sun <york.sun@nxp.com>
fsl_ddr_gen4.c 14.96 KiB