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Siarhei Siamashka authored
And also add Kconfig option for selecting ELDO3 voltage. The reason for having this option is that the Android kernel sets ELDO3 to 1.2V when powering up LCD in the case if 'lcd_if' configuration variable is set to 6 (LCD_IF_EXT_DSI) in the FEX file. Most likely to supply power for a SSD2828 chip. However on the MSI Primo81 tablet, which is using this particular 'lcd_if = 6' setup for LCD, setting the ELDO3 voltage appears to be unnecessary and it works regardless. Having no schematics of this tablet, I can only guess that 1.2V is supplied to SSD2828 in some other way. Signed-off-by:
Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Siarhei Siamashka authoredAnd also add Kconfig option for selecting ELDO3 voltage. The reason for having this option is that the Android kernel sets ELDO3 to 1.2V when powering up LCD in the case if 'lcd_if' configuration variable is set to 6 (LCD_IF_EXT_DSI) in the FEX file. Most likely to supply power for a SSD2828 chip. However on the MSI Primo81 tablet, which is using this particular 'lcd_if = 6' setup for LCD, setting the ELDO3 voltage appears to be unnecessary and it works regardless. Having no schematics of this tablet, I can only guess that 1.2V is supplied to SSD2828 in some other way. Signed-off-by:
rcc.h 2.69 KiB
/*
* (C) Copyright 2016
* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _STM32_RCC_H
#define _STM32_RCC_H
#define RCC_CR 0x00 /* clock control */
#define RCC_PLLCFGR 0x04 /* PLL configuration */
#define RCC_CFGR 0x08 /* clock configuration */
#define RCC_CIR 0x0C /* clock interrupt */
#define RCC_AHB1RSTR 0x10 /* AHB1 peripheral reset */
#define RCC_AHB2RSTR 0x14 /* AHB2 peripheral reset */
#define RCC_AHB3RSTR 0x18 /* AHB3 peripheral reset */
#define RCC_APB1RSTR 0x20 /* APB1 peripheral reset */
#define RCC_APB2RSTR 0x24 /* APB2 peripheral reset */
#define RCC_AHB1ENR 0x30 /* AHB1 peripheral clock enable */
#define RCC_AHB2ENR 0x34 /* AHB2 peripheral clock enable */
#define RCC_AHB3ENR 0x38 /* AHB3 peripheral clock enable */
#define RCC_APB1ENR 0x40 /* APB1 peripheral clock enable */
#define RCC_APB2ENR 0x44 /* APB2 peripheral clock enable */
#define RCC_AHB1LPENR 0x50 /* periph clk enable in low pwr mode */
#define RCC_AHB2LPENR 0x54 /* AHB2 periph clk enable in low pwr mode */
#define RCC_AHB3LPENR 0x58 /* AHB3 periph clk enable in low pwr mode */
#define RCC_APB1LPENR 0x60 /* APB1 periph clk enable in low pwr mode */
#define RCC_APB2LPENR 0x64 /* APB2 periph clk enable in low pwr mode */
#define RCC_BDCR 0x70 /* Backup domain control */
#define RCC_CSR 0x74 /* clock control & status */
#define RCC_SSCGR 0x80 /* spread spectrum clock generation */
#define RCC_PLLI2SCFGR 0x84 /* PLLI2S configuration */
#define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */
#define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */
#define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */
/*
* RCC AHB1ENR specific definitions
*/
#define RCC_AHB1ENR_GPIO_A_EN BIT(0)
#define RCC_AHB1ENR_GPIO_B_EN BIT(1)
#define RCC_AHB1ENR_GPIO_C_EN BIT(2)
#define RCC_AHB1ENR_GPIO_D_EN BIT(3)
#define RCC_AHB1ENR_GPIO_E_EN BIT(4)
#define RCC_AHB1ENR_GPIO_F_EN BIT(5)
#define RCC_AHB1ENR_GPIO_G_EN BIT(6)
#define RCC_AHB1ENR_GPIO_H_EN BIT(7)
#define RCC_AHB1ENR_GPIO_I_EN BIT(8)
#define RCC_AHB1ENR_GPIO_J_EN BIT(9)
#define RCC_AHB1ENR_GPIO_K_EN BIT(10)
#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)
/*
* RCC AHB3ENR specific definitions
*/
#define RCC_AHB3ENR_FMC_EN BIT(0)
/*
* RCC APB1ENR specific definitions
*/
#define RCC_APB1ENR_TIM2EN BIT(0)
#define RCC_APB1ENR_USART2EN BIT(17)
#define RCC_APB1ENR_USART3EN BIT(18)
#define RCC_APB1ENR_PWREN BIT(28)
/*
* RCC APB2ENR specific definitions */
#define RCC_APB2ENR_USART1EN BIT(4)
#define RCC_APB2ENR_USART6EN BIT(5)
#define RCC_APB2ENR_SYSCFGEN BIT(14)
#endif