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    452f50f7
    x86: coreboot: Tell u-boot about PCI bus 0 when initializing · 452f50f7
    Gabe Black authored
    
    U-boot needs a host controller or "hose" to interact with the PCI busses
    behind them. This change installs a host controller during initialization of
    the coreboot "board" which implements some of X86's basic PCI semantics. This
    relies on some existing generic code, but also duplicates a little bit of code
    from the sc520 implementation. Ideally we'd eliminate that duplication at some
    point.
    
    It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
    generic PCI configuration code what to do if it encounters a bridge,
    specifically to scan the bus on the other side of it.
    
    Signed-off-by: default avatarGabe Black <gabeblack@chromium.org>
    Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
    Acked-by: default avatarGraeme Russ <graeme.russ@gmail.com>
    452f50f7
    History
    x86: coreboot: Tell u-boot about PCI bus 0 when initializing
    Gabe Black authored
    
    U-boot needs a host controller or "hose" to interact with the PCI busses
    behind them. This change installs a host controller during initialization of
    the coreboot "board" which implements some of X86's basic PCI semantics. This
    relies on some existing generic code, but also duplicates a little bit of code
    from the sc520 implementation. Ideally we'd eliminate that duplication at some
    point.
    
    It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
    generic PCI configuration code what to do if it encounters a bridge,
    specifically to scan the bus on the other side of it.
    
    Signed-off-by: default avatarGabe Black <gabeblack@chromium.org>
    Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
    Acked-by: default avatarGraeme Russ <graeme.russ@gmail.com>