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common.h

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  • Forked from Reform / reform-boundary-uboot
    38122 commits behind the upstream repository.
    • Anton Staaf's avatar
      1e41f5ad
      cache: include asm/cache.h for ARCH_DMA_MINALIGN definition · 1e41f5ad
      Anton Staaf authored
      
      ARCH_DMA_MINALIGN will be used to allocate DMA buffers that are
      aligned correctly.  In all current cases this means that the DMA
      buffer will be aligned to at least the L1 data cache line size of
      the configured architecture.  If the board configuration file
      does not specify the architecture L1 data cache line size then the
      maximum line size of the architecture is used to align DMA buffers.
      
      Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Ilya Yanok <yanok@emcraft.com>
      Cc: Laurence Withers <lwithers@guralp.com>
      1e41f5ad
      History
      cache: include asm/cache.h for ARCH_DMA_MINALIGN definition
      Anton Staaf authored
      
      ARCH_DMA_MINALIGN will be used to allocate DMA buffers that are
      aligned correctly.  In all current cases this means that the DMA
      buffer will be aligned to at least the L1 data cache line size of
      the configured architecture.  If the board configuration file
      does not specify the architecture L1 data cache line size then the
      maximum line size of the architecture is used to align DMA buffers.
      
      Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Ilya Yanok <yanok@emcraft.com>
      Cc: Laurence Withers <lwithers@guralp.com>
    common.h 23.08 KiB