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tegra114_spi.c

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  • Forked from Reform / reform-boundary-uboot
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    • Yen Lin's avatar
      60acde43
      spi: tegra: clear RDY bit prior to every transfer · 60acde43
      Yen Lin authored
      
      The RDY bit indicates that a transfer is complete. This needs to be
      cleared by SW before every single HW transaction, rather than only
      at the start of each SW transaction (those being made up of n HW
      transactions).
      
      It seems that earlier HW may have cleared this bit autonomously when
      starting a new transfer, and hence this code was not needed in practice.
      However, this is generally a good idea in all cases. In Tegra124, the
      HW behaviour appears to have changed, and SW must explicitly clear this
      bit. Otherwise, SW will believe that transfers have completed when they
      have not, and may e.g. read stale data from the RX FIFO.
      
      Signed-off-by: default avatarYen Lin <yelin@nvidia.com>
      [swarren, rewrote commit description, unified duplicate RDY clearing code
      and moved it right before the start of the HW transaction, unconditionally
      exit loop after reading RX data, rather than checking if TX FIFO is empty,
      since it is guaranteed to be]
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Reviewed-by: default avatarJagannadha Sutradharudu Teki <jaganna@xilinx.com>
      60acde43
      History
      spi: tegra: clear RDY bit prior to every transfer
      Yen Lin authored
      
      The RDY bit indicates that a transfer is complete. This needs to be
      cleared by SW before every single HW transaction, rather than only
      at the start of each SW transaction (those being made up of n HW
      transactions).
      
      It seems that earlier HW may have cleared this bit autonomously when
      starting a new transfer, and hence this code was not needed in practice.
      However, this is generally a good idea in all cases. In Tegra124, the
      HW behaviour appears to have changed, and SW must explicitly clear this
      bit. Otherwise, SW will believe that transfers have completed when they
      have not, and may e.g. read stale data from the RX FIFO.
      
      Signed-off-by: default avatarYen Lin <yelin@nvidia.com>
      [swarren, rewrote commit description, unified duplicate RDY clearing code
      and moved it right before the start of the HW transaction, unconditionally
      exit loop after reading RX data, rather than checking if TX FIFO is empty,
      since it is guaranteed to be]
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Reviewed-by: default avatarJagannadha Sutradharudu Teki <jaganna@xilinx.com>

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