AT91 RSTC registers are battery-backuped, so their values
are not reset across power cycles. One of those registers,
the AT91_RSTC_MR register, is being modified by U-Boot, in
the ethernet initialisation routine, to generate a 500ms
user reset.

Unfortunately, this value is not being restored afterwards,
causing subsequent resets to also last for 500ms.

This long reset sequence causes problems (at least) in the
boot sequence from NOR: by the time the CPU tries to load
a program from the NOR flash, the latter is still in reset
and not yet available.

Additionaly, this patch fixes a bug in the original code which
caused the reset delay to last for 2s instead of 500ms.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>