designware.c

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11 years ago

net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN · 964ea7c1

Ian Campbell authored 11 years ago


This is required at least on ARM.

When sending instead of simply invalidating the entire descriptor, flush
as little as possible while still respecting ARCH_DMA_MINALIGN, as
requested by Alexey.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>

964ea7c1

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net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN

Ian Campbell authored 11 years ago


This is required at least on ARM.

When sending instead of simply invalidating the entire descriptor, flush
as little as possible while still respecting ARCH_DMA_MINALIGN, as
requested by Alexey.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>